diff mbox series

[Agilex7,M-series,Platform,Enablement,v1,07/16] clk: altera: Add clock support for Agilex7 M-series

Message ID 20240517052701.12949-8-tingting.meng@intel.com
State Changes Requested
Delegated to: Tom Rini
Headers show
Series [Agilex7,M-series,Platform,Enablement,v1,01/16] arch: arm: dts: Add dts and dtsi for new platform Agilex7 M-series | expand

Commit Message

Meng, Tingting May 17, 2024, 5:26 a.m. UTC 
From: Teik Heng Chong <teik.heng.chong@intel.com>

Agilex7 M-series reuse the clock driver from Agilex.

Signed-off-by: Wan Yee Lau <wan.yee.lau@intel.com>
Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
Signed-off-by: Tingting Meng <tingting.meng@intel.com>
---
 arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 +-
 arch/arm/mach-socfpga/misc.c                       | 2 +-
 drivers/clk/altera/Makefile                        | 1 +
 3 files changed, 3 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 6c9d32b9dd..77d97193f5 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -26,7 +26,7 @@  int cm_set_qspi_controller_clk_hz(u32 clk_hz);
 #include <asm/arch/clock_manager_arria10.h>
 #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
 #include <asm/arch/clock_manager_s10.h>
-#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
 #include <asm/arch/clock_manager_agilex.h>
 #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
 #include <asm/arch/clock_manager_agilex5.h>
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 79f7887519..5537445e10 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -252,7 +252,7 @@  void socfpga_get_managers_addr(void)
 	if (ret)
 		hang();
 
-#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
 	ret = socfpga_get_base_addr("intel,agilex-clkmgr",
 				    &socfpga_clkmgr_base);
 #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 61ffa4179a..858f828e53 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -4,6 +4,7 @@ 
 #
 
 obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
+obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += clk-agilex.o
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
 obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
 obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o