[v2,8/8] arm: dts: k3-*-ddr: Add ss_cfg reg entry

Message ID	20240510084707.1903133-9-s-k6@ti.com
State	New
Delegated to:	Tom Rini
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Santhosh Kumar K <s-k6@ti.com> To: <trini@konsulko.com>, <nm@ti.com>, <vigneshr@ti.com>, <bb@ti.com>, <u-kumar1@ti.com>, <m-chawdhry@ti.com> CC: <u-boot@lists.denx.de>, <n-francis@ti.com>, <s-k6@ti.com> Subject: [PATCH v2 8/8] arm: dts: k3-*-ddr: Add ss_cfg reg entry Date: Fri, 10 May 2024 14:17:07 +0530 Message-ID: <20240510084707.1903133-9-s-k6@ti.com> In-Reply-To: <20240510084707.1903133-1-s-k6@ti.com> References: <20240510084707.1903133-1-s-k6@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: list Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	ECC Series \| expand [v2,0/8] ECC Series [v2,1/8] ram: k3-ddrss: Use the DDR controller BIST engine for ECC priming [v2,2/8] ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve 'calculations restricted to… [v2,3/8] ram: k3-ddrss: Setup ECC region start and range [v2,4/8] ram: k3-ddrss: Enable ECC interrupts [v2,5/8] drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECC [v2,6/8] configs: j7_evm_r5_defconfig: Set NR_DRAM_BANKS to 2 [v2,7/8] board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC i… [v2,8/8] arm: dts: k3--ddr: Add ss_cfg reg entry

Message ID

20240510084707.1903133-9-s-k6@ti.com

State

New

Delegated to:

Tom Rini

Headers

From: Santhosh Kumar K <s-k6@ti.com>
To: <trini@konsulko.com>, <nm@ti.com>, <vigneshr@ti.com>, <bb@ti.com>,
 <u-kumar1@ti.com>, <m-chawdhry@ti.com>
CC: <u-boot@lists.denx.de>, <n-francis@ti.com>, <s-k6@ti.com>
Subject: [PATCH v2 8/8] arm: dts: k3-*-ddr: Add ss_cfg reg entry
Date: Fri, 10 May 2024 14:17:07 +0530
Message-ID: <20240510084707.1903133-9-s-k6@ti.com>
In-Reply-To: <20240510084707.1903133-1-s-k6@ti.com>
References: <20240510084707.1903133-1-s-k6@ti.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
Precedence: list
Errors-To: u-boot-bounces@lists.denx.de
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>

Series

ECC Series | expand

Commit Message

Santhosh Kumar K May 10, 2024, 8:47 a.m. UTC

Add ss_cfg memory region which maps the DDRSS configuration region
for the memory controller node.

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
---
 arch/arm/dts/k3-am62a-ddr.dtsi  |  7 ++++---
 arch/arm/dts/k3-j721s2-ddr.dtsi | 12 ++++++++----
 arch/arm/dts/k3-j784s4-ddr.dtsi | 24 ++++++++++++++++--------
 3 files changed, 28 insertions(+), 15 deletions(-)

diff --git a/arch/arm/dts/k3-am62a-ddr.dtsi b/arch/arm/dts/k3-am62a-ddr.dtsi
index 8629ea45b847..42e41f78505a 100644
--- a/arch/arm/dts/k3-am62a-ddr.dtsi
+++ b/arch/arm/dts/k3-am62a-ddr.dtsi
@@ -4,11 +4,12 @@ 
  */
 
 / {
-	memorycontroller: memory-controller@f308000 {
+	memorycontroller: memory-controller@f300000 {
 		compatible = "ti,am62a-ddrss";
 		reg = <0x00 0x0f308000 0x00 0x4000>,
-		      <0x00 0x43014000 0x00 0x100>;
-		reg-names = "cfg", "ctrl_mmr_lp4";
+		      <0x00 0x43014000 0x00 0x100>,
+		      <0x00 0x0f300000 0x00 0x200>;
+		reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
 		ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
 		ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
 		ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
diff --git a/arch/arm/dts/k3-j721s2-ddr.dtsi b/arch/arm/dts/k3-j721s2-ddr.dtsi
index 345e2b84f9e8..9764085163c4 100644
--- a/arch/arm/dts/k3-j721s2-ddr.dtsi
+++ b/arch/arm/dts/k3-j721s2-ddr.dtsi
@@ -5,6 +5,8 @@ 
 
 &main_navss {
 	ranges = <0x00 0x00114000 0x00 0x00114000 0x00 0x00000100>, // ctrl_mmr_lpr
+		 <0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0
+		 <0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1
 		 <0x00 0x02990000 0x00 0x02990000 0x00 0x00004000>, // ddr0 cfg
 		 <0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg
 		 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
@@ -24,8 +26,9 @@ 
 		memorycontroller0: memorycontroller@2990000 {
 			compatible = "ti,j721s2-ddrss";
 			reg = <0x0 0x02990000 0x0 0x4000>,
-			      <0x0 0x0114000 0x0 0x100>;
-			reg-names = "cfg", "ctrl_mmr_lp4";
+			      <0x0 0x0114000 0x0 0x100>,
+			      <0x0 0x02980000 0x0 0x200>;
+			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
 			power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>,
 				<&k3_pds 96 TI_SCI_PD_SHARED>;
 			clocks = <&k3_clks 138 0>, <&k3_clks 43 2>;
@@ -2232,8 +2235,9 @@ 
 		memorycontroller1: memorycontroller@29b0000 {
 			compatible = "ti,j721s2-ddrss";
 			reg = <0x0 0x029b0000 0x0 0x4000>,
-			      <0x0 0x0114000 0x0 0x100>;
-			reg-names = "cfg", "ctrl_mmr_lp4";
+			      <0x0 0x0114000 0x0 0x100>,
+			      <0x0 0x029a0000 0x0 0x200>;
+			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
 			power-domains = <&k3_pds 139 TI_SCI_PD_SHARED>,
 				<&k3_pds 97 TI_SCI_PD_SHARED>;
 			clocks = <&k3_clks 139 0>, <&k3_clks 43 2>;
diff --git a/arch/arm/dts/k3-j784s4-ddr.dtsi b/arch/arm/dts/k3-j784s4-ddr.dtsi
index 1c3242b0870c..fc74c539331e 100644
--- a/arch/arm/dts/k3-j784s4-ddr.dtsi
+++ b/arch/arm/dts/k3-j784s4-ddr.dtsi
@@ -9,6 +9,10 @@ 
 		 <0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg
 		 <0x00 0x029d0000 0x00 0x029d0000 0x00 0x00004000>, // ddr2 cfg
 		 <0x00 0x029f0000 0x00 0x029f0000 0x00 0x00004000>, // ddr3 cfg
+		 <0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0
+		 <0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1
+		 <0x00 0x029c0000 0x00 0x029c0000 0x00 0x00000200>, // ss cfg 2
+		 <0x00 0x029e0000 0x00 0x029e0000 0x00 0x00000200>, // ss cfg 3
 		 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
 
 	msmc0: msmc {
@@ -26,8 +30,9 @@ 
 		memorycontroller0: memorycontroller@2990000 {
 			compatible = "ti,j721s2-ddrss";
 			reg = <0x0 0x02990000 0x0 0x4000>,
-			      <0x0 0x0114000 0x0 0x100>;
-			reg-names = "cfg", "ctrl_mmr_lp4";
+			      <0x0 0x0114000 0x0 0x100>,
+			      <0x0 0x02980000 0x0 0x200>;
+			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
 			power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>,
 				<&k3_pds 131 TI_SCI_PD_SHARED>;
 			clocks = <&k3_clks 191 1>, <&k3_clks 78 2>;
@@ -2234,8 +2239,9 @@ 
 		memorycontroller1: memorycontroller@29b0000 {
 			compatible = "ti,j721s2-ddrss";
 			reg = <0x0 0x029b0000 0x0 0x4000>,
-			      <0x0 0x0114000 0x0 0x100>;
-			reg-names = "cfg", "ctrl_mmr_lp4";
+			      <0x0 0x0114000 0x0 0x100>,
+			      <0x0 0x029a0000 0x0 0x200>;
+			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
 			power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>,
 				<&k3_pds 132 TI_SCI_PD_SHARED>;
 			clocks = <&k3_clks 192 1>, <&k3_clks 78 2>;
@@ -4442,8 +4448,9 @@ 
 		memorycontroller2: memorycontroller@29d0000 {
 			compatible = "ti,j721s2-ddrss";
 			reg = <0x0 0x029d0000 0x0 0x4000>,
-			      <0x0 0x0114000 0x0 0x100>;
-			reg-names = "cfg", "ctrl_mmr_lp4";
+			      <0x0 0x0114000 0x0 0x100>,
+			      <0x0 0x029c0000 0x0 0x200>;
+			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
 			power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>,
 				<&k3_pds 133 TI_SCI_PD_SHARED>;
 			clocks = <&k3_clks 193 1>, <&k3_clks 78 2>;
@@ -6650,8 +6657,9 @@ 
 		memorycontroller3: memorycontroller@29f0000 {
 			compatible = "ti,j721s2-ddrss";
 			reg = <0x0 0x029f0000 0x0 0x4000>,
-			      <0x0 0x0114000 0x0 0x100>;
-			reg-names = "cfg", "ctrl_mmr_lp4";
+			      <0x0 0x0114000 0x0 0x100>,
+			      <0x0 0x29e0000 0x0 0x200>;
+			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
 			power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>,
 				<&k3_pds 139 TI_SCI_PD_SHARED>;
 			clocks = <&k3_clks 194 1>, <&k3_clks 78 2>;

[v2,8/8] arm: dts: k3-*-ddr: Add ss_cfg reg entry

Commit Message

Patch