@@ -20,6 +20,7 @@
#define ZYNQ_DEV_CFG_CTRL_SPIDEM BIT(5)
#define ZYNQ_DEV_CFG_CTRL_SPNIDEN BIT(6)
#define ZYNQ_DEV_CFG_CTRL_JTAG_CHAIN_DIS BIT(23)
+#define ZYNQ_DEV_CFG_LOCK_DBG_LOCK BIT(0)
#define ZYNQ_SILICON_VER_MASK 0xF0000000
#define ZYNQ_SILICON_VER_SHIFT 28
@@ -93,6 +94,15 @@ void zynq_enable_jtag(void)
writel(v, &devcfg_base->ctrl);
}
+void zynq_lock_jtag(void)
+{
+ unsigned int v;
+
+ v = readl(&devcfg_base->lock);
+ v |= ZYNQ_DEV_CFG_LOCK_DBG_LOCK;
+ writel(v, &devcfg_base->lock);
+}
+
unsigned int zynq_get_silicon_version(void)
{
return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK)
@@ -16,6 +16,7 @@ extern u32 zynq_slcr_get_idcode(void);
extern int zynq_slcr_get_mio_pin_status(const char *periph);
extern void zynq_ddrc_init(void);
extern void zynq_enable_jtag(void);
+extern void zynq_lock_jtag(void);
extern unsigned int zynq_get_silicon_version(void);
extern unsigned int zynq_get_mulitboot_addr(void);
extern void zynq_set_mulitboot_addr(unsigned int);