@@ -14,8 +14,9 @@
#include <asm/arch/ps7_init_gpl.h>
#include <asm/arch/sys_proto.h>
-#define ZYNQ_SILICON_VER_MASK 0xF0000000
-#define ZYNQ_SILICON_VER_SHIFT 28
+#define ZYNQ_SILICON_VER_MASK 0xF0000000
+#define ZYNQ_SILICON_VER_SHIFT 28
+#define ZYNQ_MULTIBOOT_ADDR_MASK 0x00001FFF
#if CONFIG_IS_ENABLED(FPGA)
xilinx_desc fpga = {
@@ -79,6 +80,20 @@ unsigned int zynq_get_silicon_version(void)
>> ZYNQ_SILICON_VER_SHIFT;
}
+unsigned int zynq_get_mulitboot_addr(void)
+{
+ return readl(&devcfg_base->multiboot_addr) & ZYNQ_MULTIBOOT_ADDR_MASK;
+}
+
+void zynq_set_mulitboot_addr(unsigned int value)
+{
+ unsigned int v = readl(&devcfg_base->multiboot_addr);
+
+ v &= ~ZYNQ_MULTIBOOT_ADDR_MASK;
+ v |= value & ZYNQ_MULTIBOOT_ADDR_MASK;
+ writel(v, &devcfg_base->multiboot_addr);
+}
+
void reset_cpu(void)
{
zynq_slcr_cpu_reset();
@@ -96,7 +96,8 @@ struct devcfg_regs {
u32 dma_src_len; /* 0x20 */
u32 dma_dst_len; /* 0x24 */
u32 rom_shadow; /* 0x28 */
- u32 reserved1[2];
+ u32 multiboot_addr; /* 0x2c */
+ u32 reserved1[1];
u32 unlock; /* 0x34 */
u32 reserved2[18];
u32 mctrl; /* 0x80 */
@@ -16,5 +16,7 @@ extern u32 zynq_slcr_get_idcode(void);
extern int zynq_slcr_get_mio_pin_status(const char *periph);
extern void zynq_ddrc_init(void);
extern unsigned int zynq_get_silicon_version(void);
+extern unsigned int zynq_get_mulitboot_addr(void);
+extern void zynq_set_mulitboot_addr(unsigned int);
#endif /* _SYS_PROTO_H_ */