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([188.163.112.49]) by smtp.gmail.com with ESMTPSA id m27-20020a1709060d9b00b00a2c7d34157asm14269068eji.180.2024.01.23.09.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 09:17:08 -0800 (PST) From: Svyatoslav Ryhel To: Thierry Reding , Anatolij Gustschin , Svyatoslav Ryhel , Simon Glass Cc: u-boot@lists.denx.de Subject: [PATCH v6 07/18] video: tegra20: dc: add powergate Date: Tue, 23 Jan 2024 19:16:22 +0200 Message-Id: <20240123171633.246057-8-clamor95@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240123171633.246057-1-clamor95@gmail.com> References: <20240123171633.246057-1-clamor95@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add powergate use on T114 to complete resetting of DC. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Thierry Reding --- drivers/video/tegra20/tegra-dc.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c index 35abb6fe46..9a18e38cd8 100644 --- a/drivers/video/tegra20/tegra-dc.c +++ b/drivers/video/tegra20/tegra-dc.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include "tegra-dc.h" @@ -32,6 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; struct tegra_dc_soc_info { bool has_timer; bool has_rgb; + bool has_pgate; }; /* Information about the display controller */ @@ -360,6 +362,28 @@ static int tegra_lcd_probe(struct udevice *dev) clock_disable(priv->dc_clk[0]); + if (priv->soc->has_pgate) { + uint powergate; + + if (priv->pipe) + powergate = TEGRA_POWERGATE_DISB; + else + powergate = TEGRA_POWERGATE_DIS; + + ret = tegra_powergate_power_off(powergate); + if (ret < 0) { + log_err("failed to power off DISP gate: %d", ret); + return ret; + } + + ret = tegra_powergate_sequence_power_up(powergate, + priv->dc_clk[0]); + if (ret < 0) { + log_err("failed to power up DISP gate: %d", ret); + return ret; + } + } + /* Reset everything set before */ reset_assert(&reset_ctl); mdelay(4); @@ -510,16 +534,19 @@ static const struct video_ops tegra_lcd_ops = { static const struct tegra_dc_soc_info tegra20_dc_soc_info = { .has_timer = true, .has_rgb = true, + .has_pgate = false, }; static const struct tegra_dc_soc_info tegra30_dc_soc_info = { .has_timer = false, .has_rgb = true, + .has_pgate = false, }; static const struct tegra_dc_soc_info tegra114_dc_soc_info = { .has_timer = false, .has_rgb = false, + .has_pgate = true, }; static const struct udevice_id tegra_lcd_ids[] = {