From patchwork Mon Nov 6 05:13:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuan Lim Lee X-Patchwork-Id: 1859712 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SP00M26BCz1yQY for ; Mon, 6 Nov 2023 16:14:56 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8D43486B0A; Mon, 6 Nov 2023 06:14:42 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id BB64886A8F; Mon, 6 Nov 2023 06:14:23 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by phobos.denx.de (Postfix) with ESMTP id DCA4086A8F for ; Mon, 6 Nov 2023 06:14:14 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=kuanlim.lee@starfivetech.com Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id DDCD07FE2; Mon, 6 Nov 2023 13:14:11 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 6 Nov 2023 13:14:11 +0800 Received: from localhost.localdomain (202.190.98.67) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 6 Nov 2023 13:14:09 +0800 From: Kuan Lim Lee To: CC: Kuan Lim Lee , Wei Liang Lim , Simon Glass Subject: [PATCH v2] timer: starfive: Add Starfive timer support Date: Mon, 6 Nov 2023 13:13:12 +0800 Message-ID: <20231106051335.1757-1-kuanlim.lee@starfivetech.com> X-Mailer: git-send-email 2.42.0.windows.2 MIME-Version: 1.0 X-Originating-IP: [202.190.98.67] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add timer driver in Starfive SoC. It is an timer that outside of CPU core and inside Starfive SoC. Signed-off-by: Kuan Lim Lee Signed-off-by: Wei Liang Lim Reviewed-by: Simon Glass Changes for v2: - correct driver name, comment, variable --- drivers/timer/Kconfig | 7 +++ drivers/timer/Makefile | 1 + drivers/timer/starfive-timer.c | 96 ++++++++++++++++++++++++++++++++++ 3 files changed, 104 insertions(+) create mode 100644 drivers/timer/starfive-timer.c diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 915b2af160..a98be9dfae 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -326,4 +326,11 @@ config XILINX_TIMER Select this to enable support for the timer found on any Xilinx boards (axi timer). +config STARFIVE_TIMER + bool "Starfive timer support" + depends on TIMER + help + Select this to enable support for the timer found on + Starfive SoC. + endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 1ca74805fd..1ef814970b 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -34,3 +34,4 @@ obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o obj-$(CONFIG_IMX_GPT_TIMER) += imx-gpt-timer.o obj-$(CONFIG_XILINX_TIMER) += xilinx-timer.o +obj-$(CONFIG_STARFIVE_TIMER) += starfive-timer.o diff --git a/drivers/timer/starfive-timer.c b/drivers/timer/starfive-timer.c new file mode 100644 index 0000000000..b9ba33277e --- /dev/null +++ b/drivers/timer/starfive-timer.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 StarFive, Inc. All rights reserved. + * Author: Lee Kuan Lim + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define STF_TIMER_INT_STATUS 0x00 +#define STF_TIMER_CTL 0x04 +#define STF_TIMER_LOAD 0x08 +#define STF_TIMER_ENABLE 0x10 +#define STF_TIMER_RELOAD 0x14 +#define STF_TIMER_VALUE 0x18 +#define STF_TIMER_INT_CLR 0x20 +#define STF_TIMER_INT_MASK 0x24 + +struct starfive_timer_priv { + void __iomem *base; + u32 timer_size; +}; + +static u64 notrace starfive_get_count(struct udevice *dev) +{ + struct starfive_timer_priv *priv = dev_get_priv(dev); + + /* Read decrement timer value and convert to increment value */ + return priv->timer_size - readl(priv->base + STF_TIMER_VALUE); +} + +static const struct timer_ops starfive_ops = { + .get_count = starfive_get_count, +}; + +static int starfive_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct starfive_timer_priv *priv = dev_get_priv(dev); + int timer_channel; + struct clk clk; + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + timer_channel = dev_read_u32_default(dev, "channel", 0); + priv->base = priv->base + (0x40 * timer_channel); + + /* Get clock rate from channel selectecd*/ + ret = clk_get_by_index(dev, timer_channel, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + uc_priv->clock_rate = clk_get_rate(&clk); + + /* + * Initiate timer, channel 0 + * Unmask Interrupt Mask + */ + writel(0, priv->base + STF_TIMER_INT_MASK); + /* Single run mode Setting */ + if (dev_read_bool(dev, "single-run")) + writel(1, priv->base + STF_TIMER_CTL); + /* Set Reload value */ + priv->timer_size = dev_read_u32_default(dev, "timer-size", -1U); + writel(priv->timer_size, priv->base + STF_TIMER_LOAD); + /* Enable to start timer */ + writel(1, priv->base + STF_TIMER_ENABLE); + + return 0; +} + +static const struct udevice_id starfive_ids[] = { + { .compatible = "starfive,jh8100-timers" }, + { } +}; + +U_BOOT_DRIVER(jh8100_starfive_timer) = { + .name = "starfive_timer", + .id = UCLASS_TIMER, + .of_match = starfive_ids, + .probe = starfive_probe, + .ops = &starfive_ops, + .priv_auto = sizeof(struct starfive_timer_priv), +};