| Message ID | 20231105231318.992857-2-chanho61.park@samsung.com |
|---|---|
| State | Accepted |
| Commit | 8ef2d7926f6973707164f4bd8f76bb94e80f336b |
| Delegated to: | Andes |
| Headers | show |
| Series | Support StarFive Watchdog driver | expand |
On Mon, Nov 06, 2023 at 08:13:15AM +0900, Chanho Park wrote: > Add JH7110_SYSCLK_WDT_APB and JH7110_SYSCLK_WDT_CORE clocks for JH7110 > watchdog device. > > Signed-off-by: Chanho Park <chanho61.park@samsung.com> > --- > drivers/clk/starfive/clk-jh7110.c | 9 +++++++++ > 1 file changed, 9 insertions(+) Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index a835541e48e9..a38694809a00 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -434,6 +434,15 @@ static int jh7110_syscrg_init(struct udevice *dev) starfive_clk_gate(priv->reg, "i2c5_apb", "apb0", OFFSET(JH7110_SYSCLK_I2C5_APB))); + /* Watchdog clocks */ + clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_APB), + starfive_clk_gate(priv->reg, + "wdt_apb", "apb0", + OFFSET(JH7110_SYSCLK_WDT_APB))); + clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_CORE), + starfive_clk_gate(priv->reg, + "wdt_core", "oscillator", + OFFSET(JH7110_SYSCLK_WDT_CORE))); /* enable noc_bus_stg_axi clock */ if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk))
Add JH7110_SYSCLK_WDT_APB and JH7110_SYSCLK_WDT_CORE clocks for JH7110 watchdog device. Signed-off-by: Chanho Park <chanho61.park@samsung.com> --- drivers/clk/starfive/clk-jh7110.c | 9 +++++++++ 1 file changed, 9 insertions(+)