From patchwork Sat Jul 15 07:40:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 1808084 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4R30dw0Qjsz20bY for ; Sat, 15 Jul 2023 17:41:24 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CDB1985E7D; Sat, 15 Jul 2023 09:41:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=ziswiler.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id D314C857D0; Sat, 15 Jul 2023 09:41:09 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mout.perfora.net (mout.perfora.net [74.208.4.197]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 156088585E for ; Sat, 15 Jul 2023 09:41:06 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=ziswiler.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=marcel@ziswiler.com Received: from toolbox.int.toradex.com ([213.55.227.4]) by mrelay.perfora.net (mreueus003 [74.208.5.2]) with ESMTPSA (Nemesis) id 0Lr0UP-1pgrR028dH-00eZTp; Sat, 15 Jul 2023 09:41:01 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Cc: Bryan Brattlof , Marcel Ziswiler , Tom Rini Subject: [PATCH v3 2/3] arm: mach-k3: am62: fix 2nd mux option of clkout0 Date: Sat, 15 Jul 2023 09:40:49 +0200 Message-Id: <20230715074050.941051-3-marcel@ziswiler.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230715074050.941051-1-marcel@ziswiler.com> References: <20230715074050.941051-1-marcel@ziswiler.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:vuFA9GCw2noAY1xvULfNE28hSbLLPQcEcgAMTcmxrtzrG12REjO 8QfWBwvebH/WPl4YIasiPeGcVeeSE3Pzh8NDK9c0RRZ2m0bkYNXsi5tCiTnBOnYAB+PCQTN krjkeB6vUk1E39MT0Hrw50JKsERyJLbaO5REqWpAkfGxlqF4jDLhHNgcYsBouj1mS12E1PX Sj5WIc3DiHAzhmiVTSQDQ== UI-OutboundReport: notjunk:1;M01:P0:wHSE3MQ91fE=;bKaEQKSqCN/ff4+lL6uhI/YcSWB HKlRLTSigH85IbahgG8928OQeHh3INKj4UhfyGfrivUk9QGdVdWeoeMxo0htKVIPxxuQbJe+v EzBTerBj55sVxV/leMZsEblzGs320817tYox/v9JCcutGW3drTOrmW5EMQi6vVrFvzk5q2xrv Zx6dxyRL9lw8kOZPU9mm2pn8CzJbN04/gIwtm+RFJ/ZeK+ZuE5P2As/y0l/dgDfA1cVWXb8ft 38ZFb3qi2Ph1PhhJidknY4Fr2w/rVNqK6AWDslJKx3e8E3e7QJA/2scWcamqOe2uCsE9M8/dS HVCJsak5+bInaKaOHWeov8Zkpmy6z4WWSMsfjFdV7gczeOZhk08RlVW75t1C58bP/C0zPBpfX vfmlPY+Dgip86NLbpYj9IiXwGTqlBFHii0lrDnm0eOxGht2ttGPunys3N/QILyZQ5jtu6dXTp zXviHM5C8IFrg9c16eAC5JmpKk9DNnfNRFw0nG1wcSBHzL3Lolt1nOs++TBaifTnV/s1RdMZB iJvHAFNjZc60x2Zg0Iou+FSWj+Xuo5VuiLYEXt1lRZNB+I9chgH1ecYhkpwQCLvyAyS1TYcPR h0eEoaHJ2zVI1bH83T8p/eT9HZsZYvd+sWIN1qWUhC8Bll0TmhnsD2b0DSsLeSSKaODn81nUL b5fJL8iGiVCDQe5xq4LO8dKYa/8iAgeBWDWsJtmgSQ== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Marcel Ziswiler Fix second mux option of clkout0 which should really be DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10 rather than twice the same according to [1]. [1] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html#clocks-for-board0-device Signed-off-by: Marcel Ziswiler Reviewed-by: Bryan Brattlof --- (no changes since v2) Changes in v2: - Add Bryan's reviewed-by tag. Thanks! arch/arm/mach-k3/am62x/clk-data.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-k3/am62x/clk-data.c b/arch/arm/mach-k3/am62x/clk-data.c index c0881778fe7..d7bfed0e031 100644 --- a/arch/arm/mach-k3/am62x/clk-data.c +++ b/arch/arm/mach-k3/am62x/clk-data.c @@ -57,7 +57,7 @@ static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { static const char * const clkout0_ctrl_out0_parents[] = { "hsdiv4_16fft_main_2_hsdivout1_clk", - "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk10", }; static const char * const clk_32k_rc_sel_out0_parents[] = { @@ -195,6 +195,7 @@ static const struct clk_data clk_list[] = { CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), @@ -313,7 +314,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 20, "clkout0_ctrl_out0"), DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk10"), DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 25, "board_0_ddr0_ck0_out"), DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),