| Message ID | 20230529045954.21689-1-cnsztl@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Kever Yang |
| Headers | show |
| Series | [v2,1/2] rockchip: rk3568: Add support for FriendlyARM NanoPi R5S | expand |
On 2023/5/29 12:59, Tianling Shen wrote: > FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device. > > Board Specifications > - Rockchip RK3568 > - 2 or 4GB LPDDR4X > - 8GB or 16GB eMMC, SD card slot > - GbE LAN (Native) > - 2x 2.5G LAN (PCIe) > - M.2 Connector > - HDMI 2.0, MIPI DSI/CSI > - 2xUSB 3.0 Host > - USB Type C PD, 5V/9V/12V > - GPIO: 12-pin 0.5mm FPC connector > > The device tree is taken from kernel v6.4-rc1. > > Signed-off-by: Tianling Shen <cnsztl@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Thanks, - Kever > --- > > No changes in v2. > > --- > arch/arm/dts/Makefile | 1 + > arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 33 ++ > arch/arm/dts/rk3568-nanopi-r5s.dts | 136 +++++ > arch/arm/dts/rk3568-nanopi-r5s.dtsi | 590 +++++++++++++++++++++ > board/rockchip/evb_rk3568/MAINTAINERS | 8 + > configs/nanopi-r5s-rk3568_defconfig | 90 ++++ > 6 files changed, 858 insertions(+) > create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi > create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts > create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dtsi > create mode 100644 configs/nanopi-r5s-rk3568_defconfig > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index 480269fa60..e2eda3ffcb 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -169,6 +169,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ > rk3566-anbernic-rgxx3.dtb \ > rk3566-radxa-cm3-io.dtb \ > rk3568-evb.dtb \ > + rk3568-nanopi-r5s.dtb \ > rk3568-rock-3a.dtb > > dtb-$(CONFIG_ROCKCHIP_RK3588) += \ > diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi > new file mode 100644 > index 0000000000..b37ad1e72d > --- /dev/null > +++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi > @@ -0,0 +1,33 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT > +/* > + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. > + * (http://www.friendlyelec.com) > + * > + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> > + */ > + > +#include "rk356x-u-boot.dtsi" > + > +/ { > + chosen { > + stdout-path = &uart2; > + u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; > + }; > +}; > + > +&sdhci { > + cap-mmc-highspeed; > + mmc-hs200-1_8v; > +}; > + > +&sdmmc0 { > + bus-width = <4>; > + bootph-pre-ram; > + u-boot,spl-fifo-mode; > +}; > + > +&uart2 { > + clock-frequency = <24000000>; > + bootph-pre-ram; > + status = "okay"; > +}; > diff --git a/arch/arm/dts/rk3568-nanopi-r5s.dts b/arch/arm/dts/rk3568-nanopi-r5s.dts > new file mode 100644 > index 0000000000..b6ad8328c7 > --- /dev/null > +++ b/arch/arm/dts/rk3568-nanopi-r5s.dts > @@ -0,0 +1,136 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT > +/* > + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. > + * (http://www.friendlyelec.com) > + * > + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> > + */ > + > +/dts-v1/; > +#include "rk3568-nanopi-r5s.dtsi" > + > +/ { > + model = "FriendlyElec NanoPi R5S"; > + compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568"; > + > + aliases { > + ethernet0 = &gmac0; > + }; > + > + gpio-leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>; > + > + led-lan1 { > + color = <LED_COLOR_ID_GREEN>; > + function = LED_FUNCTION_LAN; > + function-enumerator = <1>; > + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; > + }; > + > + led-lan2 { > + color = <LED_COLOR_ID_GREEN>; > + function = LED_FUNCTION_LAN; > + function-enumerator = <2>; > + gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; > + }; > + > + power_led: led-power { > + color = <LED_COLOR_ID_RED>; > + function = LED_FUNCTION_POWER; > + linux,default-trigger = "heartbeat"; > + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; > + }; > + > + led-wan { > + color = <LED_COLOR_ID_GREEN>; > + function = LED_FUNCTION_WAN; > + gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; > + }; > + }; > +}; > + > +&gmac0 { > + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; > + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; > + assigned-clock-rates = <0>, <125000000>; > + clock_in_out = "output"; > + phy-handle = <&rgmii_phy0>; > + phy-mode = "rgmii"; > + pinctrl-names = "default"; > + pinctrl-0 = <&gmac0_miim > + &gmac0_tx_bus2 > + &gmac0_rx_bus2 > + &gmac0_rgmii_clk > + &gmac0_rgmii_bus>; > + snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; > + snps,reset-active-low; > + /* Reset time is 15ms, 50ms for rtl8211f */ > + snps,reset-delays-us = <0 15000 50000>; > + tx_delay = <0x3c>; > + rx_delay = <0x2f>; > + status = "okay"; > +}; > + > +&mdio0 { > + rgmii_phy0: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + pinctrl-0 = <ð_phy0_reset_pin>; > + pinctrl-names = "default"; > + }; > +}; > + > +&pcie2x1 { > + num-lanes = <1>; > + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; > + status = "okay"; > +}; > + > +&pcie30phy { > + data-lanes = <1 2>; > + status = "okay"; > +}; > + > +&pcie3x1 { > + num-lanes = <1>; > + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; > + vpcie3v3-supply = <&vcc3v3_pcie>; > + status = "okay"; > +}; > + > +&pcie3x2 { > + num-lanes = <1>; > + num-ib-windows = <8>; > + num-ob-windows = <8>; > + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; > + vpcie3v3-supply = <&vcc3v3_pcie>; > + status = "okay"; > +}; > + > +&pinctrl { > + gmac0 { > + eth_phy0_reset_pin: eth-phy0-reset-pin { > + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; > + }; > + }; > + > + gpio-leds { > + lan1_led_pin: lan1-led-pin { > + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + > + lan2_led_pin: lan2-led-pin { > + rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + > + power_led_pin: power-led-pin { > + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + > + wan_led_pin: wan-led-pin { > + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + }; > +}; > diff --git a/arch/arm/dts/rk3568-nanopi-r5s.dtsi b/arch/arm/dts/rk3568-nanopi-r5s.dtsi > new file mode 100644 > index 0000000000..58ba328ea7 > --- /dev/null > +++ b/arch/arm/dts/rk3568-nanopi-r5s.dtsi > @@ -0,0 +1,590 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT > +/* > + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. > + * (http://www.friendlyelec.com) > + * > + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> > + */ > + > +/dts-v1/; > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/input/input.h> > +#include <dt-bindings/leds/common.h> > +#include <dt-bindings/pinctrl/rockchip.h> > +#include <dt-bindings/soc/rockchip,vop2.h> > +#include "rk3568.dtsi" > + > +/ { > + aliases { > + mmc0 = &sdmmc0; > + mmc1 = &sdhci; > + }; > + > + chosen: chosen { > + stdout-path = "serial2:1500000n8"; > + }; > + > + hdmi-con { > + compatible = "hdmi-connector"; > + type = "a"; > + > + port { > + hdmi_con_in: endpoint { > + remote-endpoint = <&hdmi_out_con>; > + }; > + }; > + }; > + > + vdd_usbc: vdd-usbc-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "vdd_usbc"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + }; > + > + vcc3v3_sys: vcc3v3-sys-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "vcc3v3_sys"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + vin-supply = <&vdd_usbc>; > + }; > + > + vcc5v0_sys: vcc5v0-sys-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "vcc5v0_sys"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + vin-supply = <&vdd_usbc>; > + }; > + > + vcc3v3_pcie: vcc3v3-pcie-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "vcc3v3_pcie"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + enable-active-high; > + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; > + startup-delay-us = <200000>; > + vin-supply = <&vcc5v0_sys>; > + }; > + > + vcc5v0_usb: vcc5v0-usb-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "vcc5v0_usb"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + vin-supply = <&vdd_usbc>; > + }; > + > + vcc5v0_usb_host: vcc5v0-usb-host-regulator { > + compatible = "regulator-fixed"; > + enable-active-high; > + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; > + pinctrl-names = "default"; > + pinctrl-0 = <&vcc5v0_usb_host_en>; > + regulator-name = "vcc5v0_usb_host"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + vin-supply = <&vcc5v0_usb>; > + }; > + > + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { > + compatible = "regulator-fixed"; > + enable-active-high; > + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; > + pinctrl-names = "default"; > + pinctrl-0 = <&vcc5v0_usb_otg_en>; > + regulator-name = "vcc5v0_usb_otg"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + vin-supply = <&vcc5v0_usb>; > + }; > + > + pcie30_avdd0v9: pcie30-avdd0v9-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "pcie30_avdd0v9"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <900000>; > + regulator-max-microvolt = <900000>; > + vin-supply = <&vcc3v3_sys>; > + }; > + > + pcie30_avdd1v8: pcie30-avdd1v8-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "pcie30_avdd1v8"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + vin-supply = <&vcc3v3_sys>; > + }; > +}; > + > +&combphy0 { > + status = "okay"; > +}; > + > +&combphy1 { > + status = "okay"; > +}; > + > +&combphy2 { > + status = "okay"; > +}; > + > +&cpu0 { > + cpu-supply = <&vdd_cpu>; > +}; > + > +&cpu1 { > + cpu-supply = <&vdd_cpu>; > +}; > + > +&cpu2 { > + cpu-supply = <&vdd_cpu>; > +}; > + > +&cpu3 { > + cpu-supply = <&vdd_cpu>; > +}; > + > +&gpu { > + mali-supply = <&vdd_gpu>; > + status = "okay"; > +}; > + > +&hdmi { > + avdd-0v9-supply = <&vdda0v9_image>; > + avdd-1v8-supply = <&vcca1v8_image>; > + status = "okay"; > +}; > + > +&hdmi_in { > + hdmi_in_vp0: endpoint { > + remote-endpoint = <&vp0_out_hdmi>; > + }; > +}; > + > +&hdmi_out { > + hdmi_out_con: endpoint { > + remote-endpoint = <&hdmi_con_in>; > + }; > +}; > + > +&hdmi_sound { > + status = "okay"; > +}; > + > +&i2c0 { > + status = "okay"; > + > + vdd_cpu: regulator@1c { > + compatible = "tcs,tcs4525"; > + reg = <0x1c>; > + fcs,suspend-voltage-selector = <1>; > + regulator-name = "vdd_cpu"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <1150000>; > + regulator-ramp-delay = <2300>; > + vin-supply = <&vcc5v0_sys>; > + > + regulator-state-mem { > + regulator-off-in-suspend; > + }; > + }; > + > + rk809: pmic@20 { > + compatible = "rockchip,rk809"; > + reg = <0x20>; > + interrupt-parent = <&gpio0>; > + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; > + #clock-cells = <1>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pmic_int>; > + rockchip,system-power-controller; > + vcc1-supply = <&vcc3v3_sys>; > + vcc2-supply = <&vcc3v3_sys>; > + vcc3-supply = <&vcc3v3_sys>; > + vcc4-supply = <&vcc3v3_sys>; > + vcc5-supply = <&vcc3v3_sys>; > + vcc6-supply = <&vcc3v3_sys>; > + vcc7-supply = <&vcc3v3_sys>; > + vcc8-supply = <&vcc3v3_sys>; > + vcc9-supply = <&vcc3v3_sys>; > + wakeup-source; > + > + regulators { > + vdd_logic: DCDC_REG1 { > + regulator-name = "vdd_logic"; > + regulator-always-on; > + regulator-boot-on; > + regulator-init-microvolt = <900000>; > + regulator-initial-mode = <0x2>; > + regulator-min-microvolt = <500000>; > + regulator-max-microvolt = <1350000>; > + regulator-ramp-delay = <6001>; > + > + regulator-state-mem { > + regulator-off-in-suspend; > + }; > + }; > + > + vdd_gpu: DCDC_REG2 { > + regulator-name = "vdd_gpu"; > + regulator-always-on; > + regulator-init-microvolt = <900000>; > + regulator-initial-mode = <0x2>; > + regulator-min-microvolt = <500000>; > + regulator-max-microvolt = <1350000>; > + regulator-ramp-delay = <6001>; > + > + regulator-state-mem { > + regulator-off-in-suspend; > + }; > + }; > + > + vcc_ddr: DCDC_REG3 { > + regulator-name = "vcc_ddr"; > + regulator-always-on; > + regulator-boot-on; > + regulator-initial-mode = <0x2>; > + > + regulator-state-mem { > + regulator-on-in-suspend; > + }; > + }; > + > + vdd_npu: DCDC_REG4 { > + regulator-name = "vdd_npu"; > + regulator-init-microvolt = <900000>; > + regulator-initial-mode = <0x2>; > + regulator-min-microvolt = <500000>; > + regulator-max-microvolt = <1350000>; > + regulator-ramp-delay = <6001>; > + > + regulator-state-mem { > + regulator-off-in-suspend; > + }; > + }; > + > + vcc_1v8: DCDC_REG5 { > + regulator-name = "vcc_1v8"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + > + regulator-state-mem { > + regulator-off-in-suspend; > + }; > + }; > + > + vdda0v9_image: LDO_REG1 { > + regulator-name = "vdda0v9_image"; > + regulator-min-microvolt = <950000>; > + regulator-max-microvolt = <950000>; > + > + regulator-state-mem { > + regulator-off-in-suspend; > + }; > + }; > + > + vdda_0v9: LDO_REG2 { > + regulator-name = "vdda_0v9"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <900000>; > + regulator-max-microvolt = <900000>; > + > + regulator-state-mem { > + regulator-off-in-suspend; > + }; > + }; > + > + vdda0v9_pmu: LDO_REG3 { > + regulator-name = "vdda0v9_pmu"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <900000>; > + regulator-max-microvolt = <900000>; > + > + regulator-state-mem { > + regulator-on-in-suspend; > + regulator-suspend-microvolt = <900000>; > + }; > + }; > + > + vccio_acodec: LDO_REG4 { > + regulator-name = "vccio_acodec"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + > + regulator-state-mem { > + regulator-off-in-suspend; > + }; > + }; > + > + vccio_sd: LDO_REG5 { > + regulator-name = "vccio_sd"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + > + regulator-state-mem { > + regulator-off-in-suspend; > + }; > + }; > + > + vcc3v3_pmu: LDO_REG6 { > + regulator-name = "vcc3v3_pmu"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + > + regulator-state-mem { > + regulator-on-in-suspend; > + regulator-suspend-microvolt = <3300000>; > + }; > + }; > + > + vcca_1v8: LDO_REG7 { > + regulator-name = "vcca_1v8"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + > + regulator-state-mem { > + regulator-off-in-suspend; > + }; > + }; > + > + vcca1v8_pmu: LDO_REG8 { > + regulator-name = "vcca1v8_pmu"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + > + regulator-state-mem { > + regulator-on-in-suspend; > + regulator-suspend-microvolt = <1800000>; > + }; > + }; > + > + vcca1v8_image: LDO_REG9 { > + regulator-name = "vcca1v8_image"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + > + regulator-state-mem { > + regulator-off-in-suspend; > + }; > + }; > + > + vcc_3v3: SWITCH_REG1 { > + regulator-name = "vcc_3v3"; > + regulator-always-on; > + regulator-boot-on; > + > + regulator-state-mem { > + regulator-off-in-suspend; > + }; > + }; > + > + vcc3v3_sd: SWITCH_REG2 { > + regulator-name = "vcc3v3_sd"; > + regulator-always-on; > + regulator-boot-on; > + > + regulator-state-mem { > + regulator-off-in-suspend; > + }; > + }; > + }; > + > + }; > +}; > + > +&i2c5 { > + status = "okay"; > + > + hym8563: rtc@51 { > + compatible = "haoyu,hym8563"; > + reg = <0x51>; > + interrupt-parent = <&gpio0>; > + interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; > + #clock-cells = <0>; > + clock-output-names = "rtcic_32kout"; > + pinctrl-names = "default"; > + pinctrl-0 = <&hym8563_int>; > + wakeup-source; > + }; > +}; > + > +&i2s0_8ch { > + status = "okay"; > +}; > + > +&pcie30phy { > + data-lanes = <1 2>; > + status = "okay"; > +}; > + > +&pinctrl { > + hym8563 { > + hym8563_int: hym8563-int { > + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; > + }; > + }; > + > + pmic { > + pmic_int: pmic-int { > + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; > + }; > + }; > + > + usb { > + vcc5v0_usb_host_en: vcc5v0-usb-host-en { > + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + > + vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { > + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + }; > +}; > + > +&pmu_io_domains { > + pmuio1-supply = <&vcc3v3_pmu>; > + pmuio2-supply = <&vcc3v3_pmu>; > + vccio1-supply = <&vccio_acodec>; > + vccio3-supply = <&vccio_sd>; > + vccio4-supply = <&vcc_1v8>; > + vccio5-supply = <&vcc_3v3>; > + vccio6-supply = <&vcc_1v8>; > + vccio7-supply = <&vcc_3v3>; > + status = "okay"; > +}; > + > +&saradc { > + vref-supply = <&vcca_1v8>; > + status = "okay"; > +}; > + > +&sdhci { > + bus-width = <8>; > + max-frequency = <200000000>; > + non-removable; > + pinctrl-names = "default"; > + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; > + status = "okay"; > +}; > + > +&sdmmc0 { > + max-frequency = <150000000>; > + no-sdio; > + no-mmc; > + bus-width = <4>; > + cap-mmc-highspeed; > + cap-sd-highspeed; > + disable-wp; > + vmmc-supply = <&vcc3v3_sd>; > + vqmmc-supply = <&vccio_sd>; > + pinctrl-names = "default"; > + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; > + status = "okay"; > +}; > + > +&tsadc { > + rockchip,hw-tshut-mode = <1>; > + rockchip,hw-tshut-polarity = <0>; > + status = "okay"; > +}; > + > +&uart2 { > + status = "okay"; > +}; > + > +&usb_host0_ehci { > + status = "okay"; > +}; > + > +&usb_host0_ohci { > + status = "okay"; > +}; > + > +&usb_host0_xhci { > + extcon = <&usb2phy0>; > + dr_mode = "host"; > + status = "okay"; > +}; > + > +&usb_host1_ehci { > + status = "okay"; > +}; > + > +&usb_host1_ohci { > + status = "okay"; > +}; > + > +&usb_host1_xhci { > + status = "okay"; > +}; > + > +&usb2phy0 { > + status = "okay"; > +}; > + > +&usb2phy0_host { > + phy-supply = <&vcc5v0_usb_host>; > + status = "okay"; > +}; > + > +&usb2phy0_otg { > + status = "okay"; > +}; > + > +&usb2phy1 { > + status = "okay"; > +}; > + > +&usb2phy1_host { > + phy-supply = <&vcc5v0_usb_otg>; > + status = "okay"; > +}; > + > +&usb2phy1_otg { > + status = "okay"; > +}; > + > +&vop { > + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; > + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; > + status = "okay"; > +}; > + > +&vop_mmu { > + status = "okay"; > +}; > + > +&vp0 { > + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { > + reg = <ROCKCHIP_VOP2_EP_HDMI0>; > + remote-endpoint = <&hdmi_in_vp0>; > + }; > +}; > diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS > index 6b2e7c7575..9222682461 100644 > --- a/board/rockchip/evb_rk3568/MAINTAINERS > +++ b/board/rockchip/evb_rk3568/MAINTAINERS > @@ -7,6 +7,14 @@ F: configs/evb-rk3568_defconfig > F: arch/arm/dts/rk3568-evb-boot.dtsi > F: arch/arm/dts/rk3568-evb.dts > > +NANOPI-R5S > +M: Tianling Shen <cnsztl@gmail.com> > +S: Maintained > +F: configs/nanopi-r5s-rk3568_defconfig > +F: arch/arm/dts/rk3568-nanopi-r5s.dts > +F: arch/arm/dts/rk3568-nanopi-r5s.dtsi > +F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi > + > RADXA-CM3 > M: Jagan Teki <jagan@amarulasolutions.com> > S: Maintained > diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig > new file mode 100644 > index 0000000000..041fa6d84f > --- /dev/null > +++ b/configs/nanopi-r5s-rk3568_defconfig > @@ -0,0 +1,90 @@ > +CONFIG_ARM=y > +CONFIG_SKIP_LOWLEVEL_INIT=y > +CONFIG_COUNTER_FREQUENCY=24000000 > +CONFIG_ARCH_ROCKCHIP=y > +CONFIG_TEXT_BASE=0x00a00000 > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_NR_DRAM_BANKS=2 > +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y > +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 > +CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" > +CONFIG_ROCKCHIP_RK3568=y > +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y > +CONFIG_SPL_SERIAL=y > +CONFIG_SPL_STACK_R_ADDR=0x600000 > +CONFIG_TARGET_EVB_RK3568=y > +CONFIG_SPL_STACK=0x400000 > +CONFIG_DEBUG_UART_BASE=0xFE660000 > +CONFIG_DEBUG_UART_CLOCK=24000000 > +CONFIG_SYS_LOAD_ADDR=0xc00800 > +CONFIG_DEBUG_UART=y > +CONFIG_FIT=y > +CONFIG_FIT_VERBOSE=y > +CONFIG_SPL_LOAD_FIT=y > +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb" > +# CONFIG_DISPLAY_CPUINFO is not set > +CONFIG_DISPLAY_BOARDINFO_LATE=y > +CONFIG_SPL_MAX_SIZE=0x40000 > +CONFIG_SPL_PAD_TO=0x7f8000 > +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y > +CONFIG_SPL_BSS_START_ADDR=0x4000000 > +CONFIG_SPL_BSS_MAX_SIZE=0x4000 > +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set > +CONFIG_SPL_STACK_R=y > +CONFIG_SPL_ATF=y > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_GPT=y > +CONFIG_CMD_I2C=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_USB=y > +CONFIG_CMD_USB_MASS_STORAGE=y > +CONFIG_CMD_PMIC=y > +CONFIG_CMD_REGULATOR=y > +# CONFIG_SPL_DOS_PARTITION is not set > +CONFIG_SPL_OF_CONTROL=y > +CONFIG_OF_LIVE=y > +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" > +CONFIG_SPL_DM_WARN=y > +CONFIG_SPL_REGMAP=y > +CONFIG_SPL_SYSCON=y > +CONFIG_SPL_CLK=y > +CONFIG_ROCKCHIP_GPIO=y > +CONFIG_SYS_I2C_ROCKCHIP=y > +CONFIG_MISC=y > +CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_DW=y > +CONFIG_MMC_DW_ROCKCHIP=y > +CONFIG_MMC_SDHCI=y > +CONFIG_MMC_SDHCI_SDMA=y > +CONFIG_MMC_SDHCI_ROCKCHIP=y > +CONFIG_DM_ETH=y > +CONFIG_ETH_DESIGNWARE=y > +CONFIG_GMAC_ROCKCHIP=y > +CONFIG_POWER_DOMAIN=y > +CONFIG_PHY_ROCKCHIP_INNO_USB2=y > +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y > +CONFIG_DM_PMIC=y > +CONFIG_PMIC_RK8XX=y > +CONFIG_REGULATOR_PWM=y > +CONFIG_DM_REGULATOR_FIXED=y > +CONFIG_SPL_DM_REGULATOR_FIXED=y > +CONFIG_DM_REGULATOR_GPIO=y > +CONFIG_REGULATOR_RK8XX=y > +CONFIG_PWM_ROCKCHIP=y > +CONFIG_SPL_RAM=y > +CONFIG_BAUDRATE=1500000 > +CONFIG_DEBUG_UART_SHIFT=2 > +CONFIG_SYS_NS16550_MEM32=y > +CONFIG_SYSRESET=y > +CONFIG_SYSRESET_PSCI=y > +CONFIG_USB=y > +CONFIG_USB_XHCI_HCD=y > +CONFIG_USB_XHCI_DWC3=y > +CONFIG_USB_EHCI_HCD=y > +CONFIG_USB_EHCI_GENERIC=y > +CONFIG_USB_OHCI_HCD=y > +CONFIG_USB_OHCI_GENERIC=y > +CONFIG_USB_DWC3=y > +CONFIG_ERRNO_STR=y
Hi, On 2023-05-29 06:59, Tianling Shen wrote: > FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device. > > Board Specifications > - Rockchip RK3568 > - 2 or 4GB LPDDR4X > - 8GB or 16GB eMMC, SD card slot > - GbE LAN (Native) > - 2x 2.5G LAN (PCIe) > - M.2 Connector > - HDMI 2.0, MIPI DSI/CSI > - 2xUSB 3.0 Host > - USB Type C PD, 5V/9V/12V > - GPIO: 12-pin 0.5mm FPC connector > > The device tree is taken from kernel v6.4-rc1. > > Signed-off-by: Tianling Shen <cnsztl@gmail.com> > --- > > No changes in v2. > > --- > arch/arm/dts/Makefile | 1 + > arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 33 ++ > arch/arm/dts/rk3568-nanopi-r5s.dts | 136 +++++ > arch/arm/dts/rk3568-nanopi-r5s.dtsi | 590 +++++++++++++++++++++ > board/rockchip/evb_rk3568/MAINTAINERS | 8 + > configs/nanopi-r5s-rk3568_defconfig | 90 ++++ > 6 files changed, 858 insertions(+) > create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi > create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts > create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dtsi > create mode 100644 configs/nanopi-r5s-rk3568_defconfig > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index 480269fa60..e2eda3ffcb 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -169,6 +169,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ > rk3566-anbernic-rgxx3.dtb \ > rk3566-radxa-cm3-io.dtb \ > rk3568-evb.dtb \ > + rk3568-nanopi-r5s.dtb \ > rk3568-rock-3a.dtb > > dtb-$(CONFIG_ROCKCHIP_RK3588) += \ > diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi > new file mode 100644 > index 0000000000..b37ad1e72d > --- /dev/null > +++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi > @@ -0,0 +1,33 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT > +/* > + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. > + * (http://www.friendlyelec.com) > + * > + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> > + */ > + > +#include "rk356x-u-boot.dtsi" > + > +/ { > + chosen { > + stdout-path = &uart2; > + u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; > + }; > +}; > + > +&sdhci { > + cap-mmc-highspeed; > + mmc-hs200-1_8v; > +}; Because this is a rk3568 you can probably also add: mmc-ddr-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; and a pinctrl with emmc_datastrobe according to schematic: pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; > + > +&sdmmc0 { > + bus-width = <4>; > + bootph-pre-ram; > + u-boot,spl-fifo-mode; > +}; The sdmmc0 node is not needed: - bus-width is set in linux dts - bootph-pre-ram is set in rk356x-u-boot.dtsi - u-boot,spl-fifo-mode is not needed on rk356x > + > +&uart2 { > + clock-frequency = <24000000>; > + bootph-pre-ram; Recommended to be bootph-all, in case TPL support gets added in future. > + status = "okay"; > +}; [snip] > diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS > index 6b2e7c7575..9222682461 100644 > --- a/board/rockchip/evb_rk3568/MAINTAINERS > +++ b/board/rockchip/evb_rk3568/MAINTAINERS > @@ -7,6 +7,14 @@ F: configs/evb-rk3568_defconfig > F: arch/arm/dts/rk3568-evb-boot.dtsi > F: arch/arm/dts/rk3568-evb.dts > > +NANOPI-R5S > +M: Tianling Shen <cnsztl@gmail.com> > +S: Maintained > +F: configs/nanopi-r5s-rk3568_defconfig > +F: arch/arm/dts/rk3568-nanopi-r5s.dts > +F: arch/arm/dts/rk3568-nanopi-r5s.dtsi > +F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi > + > RADXA-CM3 > M: Jagan Teki <jagan@amarulasolutions.com> > S: Maintained > diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig > new file mode 100644 > index 0000000000..041fa6d84f > --- /dev/null > +++ b/configs/nanopi-r5s-rk3568_defconfig > @@ -0,0 +1,90 @@ > +CONFIG_ARM=y > +CONFIG_SKIP_LOWLEVEL_INIT=y > +CONFIG_COUNTER_FREQUENCY=24000000 > +CONFIG_ARCH_ROCKCHIP=y > +CONFIG_TEXT_BASE=0x00a00000 > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_NR_DRAM_BANKS=2 > +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y > +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 > +CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" > +CONFIG_ROCKCHIP_RK3568=y > +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y > +CONFIG_SPL_SERIAL=y > +CONFIG_SPL_STACK_R_ADDR=0x600000 > +CONFIG_TARGET_EVB_RK3568=y > +CONFIG_SPL_STACK=0x400000 > +CONFIG_DEBUG_UART_BASE=0xFE660000 > +CONFIG_DEBUG_UART_CLOCK=24000000 > +CONFIG_SYS_LOAD_ADDR=0xc00800 > +CONFIG_DEBUG_UART=y > +CONFIG_FIT=y > +CONFIG_FIT_VERBOSE=y > +CONFIG_SPL_LOAD_FIT=y > +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb" > +# CONFIG_DISPLAY_CPUINFO is not set > +CONFIG_DISPLAY_BOARDINFO_LATE=y > +CONFIG_SPL_MAX_SIZE=0x40000 > +CONFIG_SPL_PAD_TO=0x7f8000 > +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y > +CONFIG_SPL_BSS_START_ADDR=0x4000000 > +CONFIG_SPL_BSS_MAX_SIZE=0x4000 > +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set > +CONFIG_SPL_STACK_R=y > +CONFIG_SPL_ATF=y > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_GPT=y > +CONFIG_CMD_I2C=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_USB=y > +CONFIG_CMD_USB_MASS_STORAGE=y > +CONFIG_CMD_PMIC=y > +CONFIG_CMD_REGULATOR=y > +# CONFIG_SPL_DOS_PARTITION is not set > +CONFIG_SPL_OF_CONTROL=y > +CONFIG_OF_LIVE=y > +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" > +CONFIG_SPL_DM_WARN=y > +CONFIG_SPL_REGMAP=y > +CONFIG_SPL_SYSCON=y > +CONFIG_SPL_CLK=y > +CONFIG_ROCKCHIP_GPIO=y > +CONFIG_SYS_I2C_ROCKCHIP=y > +CONFIG_MISC=y > +CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_DW=y > +CONFIG_MMC_DW_ROCKCHIP=y > +CONFIG_MMC_SDHCI=y > +CONFIG_MMC_SDHCI_SDMA=y > +CONFIG_MMC_SDHCI_ROCKCHIP=y > +CONFIG_DM_ETH=y > +CONFIG_ETH_DESIGNWARE=y > +CONFIG_GMAC_ROCKCHIP=y > +CONFIG_POWER_DOMAIN=y > +CONFIG_PHY_ROCKCHIP_INNO_USB2=y > +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y > +CONFIG_DM_PMIC=y > +CONFIG_PMIC_RK8XX=y > +CONFIG_REGULATOR_PWM=y > +CONFIG_DM_REGULATOR_FIXED=y > +CONFIG_SPL_DM_REGULATOR_FIXED=y > +CONFIG_DM_REGULATOR_GPIO=y REGULATOR_PWM and DM_REGULATOR_GPIO is not referenced in device tree. DM_REGULATOR_FIXED is selected in arch Kconfig I would recommend running moveconfig.py to clean up/re-order this file. Regards, Jonas > +CONFIG_REGULATOR_RK8XX=y > +CONFIG_PWM_ROCKCHIP=y > +CONFIG_SPL_RAM=y > +CONFIG_BAUDRATE=1500000 > +CONFIG_DEBUG_UART_SHIFT=2 > +CONFIG_SYS_NS16550_MEM32=y > +CONFIG_SYSRESET=y > +CONFIG_SYSRESET_PSCI=y > +CONFIG_USB=y > +CONFIG_USB_XHCI_HCD=y > +CONFIG_USB_XHCI_DWC3=y > +CONFIG_USB_EHCI_HCD=y > +CONFIG_USB_EHCI_GENERIC=y > +CONFIG_USB_OHCI_HCD=y > +CONFIG_USB_OHCI_GENERIC=y > +CONFIG_USB_DWC3=y > +CONFIG_ERRNO_STR=y
Hi Jonas, On Mon, May 29, 2023 at 11:45 PM Jonas Karlman <jonas@kwiboo.se> wrote: > > Hi, > > On 2023-05-29 06:59, Tianling Shen wrote: > > FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device. > > > > Board Specifications > > - Rockchip RK3568 > > - 2 or 4GB LPDDR4X > > - 8GB or 16GB eMMC, SD card slot > > - GbE LAN (Native) > > - 2x 2.5G LAN (PCIe) > > - M.2 Connector > > - HDMI 2.0, MIPI DSI/CSI > > - 2xUSB 3.0 Host > > - USB Type C PD, 5V/9V/12V > > - GPIO: 12-pin 0.5mm FPC connector > > > > The device tree is taken from kernel v6.4-rc1. > > > > Signed-off-by: Tianling Shen <cnsztl@gmail.com> > > --- > > > > No changes in v2. > > > > --- > > arch/arm/dts/Makefile | 1 + > > arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 33 ++ > > arch/arm/dts/rk3568-nanopi-r5s.dts | 136 +++++ > > arch/arm/dts/rk3568-nanopi-r5s.dtsi | 590 +++++++++++++++++++++ > > board/rockchip/evb_rk3568/MAINTAINERS | 8 + > > configs/nanopi-r5s-rk3568_defconfig | 90 ++++ > > 6 files changed, 858 insertions(+) > > create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi > > create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts > > create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dtsi > > create mode 100644 configs/nanopi-r5s-rk3568_defconfig > > > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > > index 480269fa60..e2eda3ffcb 100644 > > --- a/arch/arm/dts/Makefile > > +++ b/arch/arm/dts/Makefile > > @@ -169,6 +169,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ > > rk3566-anbernic-rgxx3.dtb \ > > rk3566-radxa-cm3-io.dtb \ > > rk3568-evb.dtb \ > > + rk3568-nanopi-r5s.dtb \ > > rk3568-rock-3a.dtb > > > > dtb-$(CONFIG_ROCKCHIP_RK3588) += \ > > diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi > > new file mode 100644 > > index 0000000000..b37ad1e72d > > --- /dev/null > > +++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi > > @@ -0,0 +1,33 @@ > > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT > > +/* > > + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. > > + * (http://www.friendlyelec.com) > > + * > > + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> > > + */ > > + > > +#include "rk356x-u-boot.dtsi" > > + > > +/ { > > + chosen { > > + stdout-path = &uart2; > > + u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; > > + }; > > +}; > > + > > +&sdhci { > > + cap-mmc-highspeed; > > + mmc-hs200-1_8v; > > +}; > > Because this is a rk3568 you can probably also add: > > mmc-ddr-1_8v; > mmc-hs400-1_8v; > mmc-hs400-enhanced-strobe; > > and a pinctrl with emmc_datastrobe according to schematic: > > pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; > > > + > > +&sdmmc0 { > > + bus-width = <4>; > > + bootph-pre-ram; > > + u-boot,spl-fifo-mode; > > +}; > > The sdmmc0 node is not needed: > - bus-width is set in linux dts > - bootph-pre-ram is set in rk356x-u-boot.dtsi > - u-boot,spl-fifo-mode is not needed on rk356x > > > + > > +&uart2 { > > + clock-frequency = <24000000>; > > + bootph-pre-ram; > > Recommended to be bootph-all, in case TPL support gets added in future. > Thank you so much for all of these explanations and suggestions! I will test them later today and send v3. Thanks, Tianling. > > + status = "okay"; > > +}; > > [snip] > > > diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS > > index 6b2e7c7575..9222682461 100644 > > --- a/board/rockchip/evb_rk3568/MAINTAINERS > > +++ b/board/rockchip/evb_rk3568/MAINTAINERS > > @@ -7,6 +7,14 @@ F: configs/evb-rk3568_defconfig > > F: arch/arm/dts/rk3568-evb-boot.dtsi > > F: arch/arm/dts/rk3568-evb.dts > > > > +NANOPI-R5S > > +M: Tianling Shen <cnsztl@gmail.com> > > +S: Maintained > > +F: configs/nanopi-r5s-rk3568_defconfig > > +F: arch/arm/dts/rk3568-nanopi-r5s.dts > > +F: arch/arm/dts/rk3568-nanopi-r5s.dtsi > > +F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi > > + > > RADXA-CM3 > > M: Jagan Teki <jagan@amarulasolutions.com> > > S: Maintained > > diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig > > new file mode 100644 > > index 0000000000..041fa6d84f > > --- /dev/null > > +++ b/configs/nanopi-r5s-rk3568_defconfig > > @@ -0,0 +1,90 @@ > > +CONFIG_ARM=y > > +CONFIG_SKIP_LOWLEVEL_INIT=y > > +CONFIG_COUNTER_FREQUENCY=24000000 > > +CONFIG_ARCH_ROCKCHIP=y > > +CONFIG_TEXT_BASE=0x00a00000 > > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > > +CONFIG_NR_DRAM_BANKS=2 > > +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y > > +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 > > +CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" > > +CONFIG_ROCKCHIP_RK3568=y > > +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y > > +CONFIG_SPL_SERIAL=y > > +CONFIG_SPL_STACK_R_ADDR=0x600000 > > +CONFIG_TARGET_EVB_RK3568=y > > +CONFIG_SPL_STACK=0x400000 > > +CONFIG_DEBUG_UART_BASE=0xFE660000 > > +CONFIG_DEBUG_UART_CLOCK=24000000 > > +CONFIG_SYS_LOAD_ADDR=0xc00800 > > +CONFIG_DEBUG_UART=y > > +CONFIG_FIT=y > > +CONFIG_FIT_VERBOSE=y > > +CONFIG_SPL_LOAD_FIT=y > > +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb" > > +# CONFIG_DISPLAY_CPUINFO is not set > > +CONFIG_DISPLAY_BOARDINFO_LATE=y > > +CONFIG_SPL_MAX_SIZE=0x40000 > > +CONFIG_SPL_PAD_TO=0x7f8000 > > +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y > > +CONFIG_SPL_BSS_START_ADDR=0x4000000 > > +CONFIG_SPL_BSS_MAX_SIZE=0x4000 > > +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > > +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set > > +CONFIG_SPL_STACK_R=y > > +CONFIG_SPL_ATF=y > > +CONFIG_CMD_GPIO=y > > +CONFIG_CMD_GPT=y > > +CONFIG_CMD_I2C=y > > +CONFIG_CMD_MMC=y > > +CONFIG_CMD_USB=y > > +CONFIG_CMD_USB_MASS_STORAGE=y > > +CONFIG_CMD_PMIC=y > > +CONFIG_CMD_REGULATOR=y > > +# CONFIG_SPL_DOS_PARTITION is not set > > +CONFIG_SPL_OF_CONTROL=y > > +CONFIG_OF_LIVE=y > > +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" > > +CONFIG_SPL_DM_WARN=y > > +CONFIG_SPL_REGMAP=y > > +CONFIG_SPL_SYSCON=y > > +CONFIG_SPL_CLK=y > > +CONFIG_ROCKCHIP_GPIO=y > > +CONFIG_SYS_I2C_ROCKCHIP=y > > +CONFIG_MISC=y > > +CONFIG_SUPPORT_EMMC_RPMB=y > > +CONFIG_MMC_DW=y > > +CONFIG_MMC_DW_ROCKCHIP=y > > +CONFIG_MMC_SDHCI=y > > +CONFIG_MMC_SDHCI_SDMA=y > > +CONFIG_MMC_SDHCI_ROCKCHIP=y > > +CONFIG_DM_ETH=y > > +CONFIG_ETH_DESIGNWARE=y > > +CONFIG_GMAC_ROCKCHIP=y > > +CONFIG_POWER_DOMAIN=y > > +CONFIG_PHY_ROCKCHIP_INNO_USB2=y > > +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y > > +CONFIG_DM_PMIC=y > > +CONFIG_PMIC_RK8XX=y > > +CONFIG_REGULATOR_PWM=y > > +CONFIG_DM_REGULATOR_FIXED=y > > +CONFIG_SPL_DM_REGULATOR_FIXED=y > > +CONFIG_DM_REGULATOR_GPIO=y > > REGULATOR_PWM and DM_REGULATOR_GPIO is not referenced in device tree. > DM_REGULATOR_FIXED is selected in arch Kconfig > > I would recommend running moveconfig.py to clean up/re-order this file. > > Regards, > Jonas > > > +CONFIG_REGULATOR_RK8XX=y > > +CONFIG_PWM_ROCKCHIP=y > > +CONFIG_SPL_RAM=y > > +CONFIG_BAUDRATE=1500000 > > +CONFIG_DEBUG_UART_SHIFT=2 > > +CONFIG_SYS_NS16550_MEM32=y > > +CONFIG_SYSRESET=y > > +CONFIG_SYSRESET_PSCI=y > > +CONFIG_USB=y > > +CONFIG_USB_XHCI_HCD=y > > +CONFIG_USB_XHCI_DWC3=y > > +CONFIG_USB_EHCI_HCD=y > > +CONFIG_USB_EHCI_GENERIC=y > > +CONFIG_USB_OHCI_HCD=y > > +CONFIG_USB_OHCI_GENERIC=y > > +CONFIG_USB_DWC3=y > > +CONFIG_ERRNO_STR=y >
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 480269fa60..e2eda3ffcb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -169,6 +169,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-anbernic-rgxx3.dtb \ rk3566-radxa-cm3-io.dtb \ rk3568-evb.dtb \ + rk3568-nanopi-r5s.dtb \ rk3568-rock-3a.dtb dtb-$(CONFIG_ROCKCHIP_RK3588) += \ diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi new file mode 100644 index 0000000000..b37ad1e72d --- /dev/null +++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> + */ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; + }; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + +&sdmmc0 { + bus-width = <4>; + bootph-pre-ram; + u-boot,spl-fifo-mode; +}; + +&uart2 { + clock-frequency = <24000000>; + bootph-pre-ram; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3568-nanopi-r5s.dts b/arch/arm/dts/rk3568-nanopi-r5s.dts new file mode 100644 index 0000000000..b6ad8328c7 --- /dev/null +++ b/arch/arm/dts/rk3568-nanopi-r5s.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> + */ + +/dts-v1/; +#include "rk3568-nanopi-r5s.dtsi" + +/ { + model = "FriendlyElec NanoPi R5S"; + compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>; + + led-lan1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + }; + + led-lan2 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; + }; + + power_led: led-power { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_POWER; + linux,default-trigger = "heartbeat"; + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + }; + + led-wan { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WAN; + gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 15ms, 50ms for rtl8211f */ + snps,reset-delays-us = <0 15000 50000>; + tx_delay = <0x3c>; + rx_delay = <0x2f>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + }; +}; + +&pcie2x1 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + num-ib-windows = <8>; + num-ob-windows = <8>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + gmac0 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + lan1_led_pin: lan1-led-pin { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan2_led_pin: lan2-led-pin { + rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + power_led_pin: power-led-pin { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/dts/rk3568-nanopi-r5s.dtsi b/arch/arm/dts/rk3568-nanopi-r5s.dtsi new file mode 100644 index 0000000000..58ba328ea7 --- /dev/null +++ b/arch/arm/dts/rk3568-nanopi-r5s.dtsi @@ -0,0 +1,590 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3568.dtsi" + +/ { + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + vdd_usbc: vdd-usbc-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd_usbc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_usbc>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_usbc>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <200000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_usbc>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + }; +}; + +&i2c5 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <0>; + clock-output-names = "rtcic_32kout"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0-usb-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1_otg { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index 6b2e7c7575..9222682461 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -7,6 +7,14 @@ F: configs/evb-rk3568_defconfig F: arch/arm/dts/rk3568-evb-boot.dtsi F: arch/arm/dts/rk3568-evb.dts +NANOPI-R5S +M: Tianling Shen <cnsztl@gmail.com> +S: Maintained +F: configs/nanopi-r5s-rk3568_defconfig +F: arch/arm/dts/rk3568-nanopi-r5s.dts +F: arch/arm/dts/rk3568-nanopi-r5s.dtsi +F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi + RADXA-CM3 M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig new file mode 100644 index 0000000000..041fa6d84f --- /dev/null +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_EVB_RK3568=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_WARN=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_POWER_DOMAIN=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_ERRNO_STR=y
FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device. Board Specifications - Rockchip RK3568 - 2 or 4GB LPDDR4X - 8GB or 16GB eMMC, SD card slot - GbE LAN (Native) - 2x 2.5G LAN (PCIe) - M.2 Connector - HDMI 2.0, MIPI DSI/CSI - 2xUSB 3.0 Host - USB Type C PD, 5V/9V/12V - GPIO: 12-pin 0.5mm FPC connector The device tree is taken from kernel v6.4-rc1. Signed-off-by: Tianling Shen <cnsztl@gmail.com> --- No changes in v2. --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 33 ++ arch/arm/dts/rk3568-nanopi-r5s.dts | 136 +++++ arch/arm/dts/rk3568-nanopi-r5s.dtsi | 590 +++++++++++++++++++++ board/rockchip/evb_rk3568/MAINTAINERS | 8 + configs/nanopi-r5s-rk3568_defconfig | 90 ++++ 6 files changed, 858 insertions(+) create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dtsi create mode 100644 configs/nanopi-r5s-rk3568_defconfig