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psci: fix use of clobbered registers in asm

Message ID 20230528000942.231907-1-CFSworks@gmail.com
State Accepted
Commit 8dc2c666808a07c2ad484ef6c4f89aa551eaf265
Delegated to: Tom Rini
Headers show
Series psci: fix use of clobbered registers in asm | expand

Commit Message

Sam Edwards May 28, 2023, 12:09 a.m. UTC
The functions `psci_get_context_id` and `psci_get_target_pc`
are written in C, so the C compiler may clobber registers r0-r3.
Do not use these registers to save data across calls.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
---
 arch/arm/cpu/armv7/psci.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Tom Rini June 21, 2023, 6:40 p.m. UTC | #1
On Sat, May 27, 2023 at 06:09:42PM -0600, Sam Edwards wrote:

> The functions `psci_get_context_id` and `psci_get_target_pc`
> are written in C, so the C compiler may clobber registers r0-r3.
> Do not use these registers to save data across calls.
> 
> Signed-off-by: Sam Edwards <CFSworks@gmail.com>

Applied to u-boot/next, thanks!
diff mbox series

Patch

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 6c066e50d9..41428728b7 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -311,11 +311,11 @@  ENTRY(psci_cpu_entry)
 	bl	psci_arch_cpu_entry
 
 	bl	psci_get_cpu_id			@ CPU ID => r0
-	mov	r2, r0				@ CPU ID => r2
 	bl	psci_get_context_id		@ context id => r0
-	mov	r1, r0				@ context id => r1
-	mov	r0, r2				@ CPU ID => r0
+	push	{r0}				@ save context id
+	bl	psci_get_cpu_id			@ CPU ID => r0
 	bl	psci_get_target_pc		@ target PC => r0
+	pop	{r1}				@ context id => r1
 	b	_do_nonsec_entry
 ENDPROC(psci_cpu_entry)