| Message ID | 20230517220239.329807-1-marex@denx.de |
|---|---|
| State | Accepted |
| Commit | b3d97f8ce34011b8928919822eb17b98477f3d72 |
| Delegated to: | Patrice Chotard |
| Headers | show |
| Series | ARM: stm32: Power cycle Buck3 in reset on DHSOM | expand |
Hi Marek, On 5/18/23 00:02, Marek Vasut wrote: > In case the DHSOM is in suspend state and either reset button is pushed > or IWDG2 triggers a watchdog reset, then DRAM initialization could fail > as follows: > > " > RAM: DDR3L 32bits 2x4Gb 533MHz > DDR invalid size : 0x4, expected 0x40000000 > DRAM init failed: -22 > ### ERROR ### Please RESET the board ### > " > > Avoid this failure by not keeping any Buck regulators enabled during reset, > let the SoC and DRAMs power cycle fully. Since the change which keeps Buck3 > VDD enabled during reset is ST specific, move this addition to ST specific > SPL board initialization so that it wouldn't affect the DHSOM . > Signed-off-by: Marek Vasut <marex@denx.de> > --- > NOTE: This is 2023.07 material > NOTE: d1a4b09de64 ("board: st: stpmic1: add function stpmic1_init") > mentions 'keep vdd on during the reset cycle (to avoid issue > when backup battery is absent)', but there is no further > description of the 'issue'. Can you please elaborate ? In the commit message of d1a4b09de643 ("board: st: stpmic1: add function stpmic1_init"), I indicated - keep vdd on during the reset cycle (to avoid issue when backup battery is absent) On ST boards we have support of cell coin to allow support of backup domain, but by default this cell are absent and the backup domain is directly powered by VDD (directly connected by resistor). We keep powered this domain to don't loss the backup domain support, to avoid to loss the information saved in backup RAM / registers, and to be abble to keep DEBUG part powered also. On this ST board, if the VDD is shut down with reset, the backup domain can't be correctly managed for reboot. And to handle correctly power OFF on ST boards with PMIC, we will don't shut down the VDD (full PMIC shut down) but we keep it. So the backup domain is loosed on ST board with STPMIC1 only when the power is removed and not for reset or for power off. > --- > Cc: Patrice Chotard <patrice.chotard@foss.st.com> > Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> > Cc: uboot-stm32@st-md-mailman.stormreply.com > --- > board/st/common/stpmic1.c | 10 +++------- > board/st/common/stpmic1.h | 2 +- > board/st/stm32mp1/spl.c | 13 +++++++++++-- > 3 files changed, 15 insertions(+), 10 deletions(-) > > diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c > index d52dce4f657..969ad484864 100644 > --- a/board/st/common/stpmic1.c > +++ b/board/st/common/stpmic1.c > @@ -185,21 +185,17 @@ static int stmpic_buck1_set(struct udevice *dev, u32 voltage_mv) > } > > /* early init of PMIC */ > -void stpmic1_init(u32 voltage_mv) > +struct udevice *stpmic1_init(u32 voltage_mv) > { > struct udevice *dev; > > if (uclass_get_device_by_driver(UCLASS_PMIC, > DM_DRIVER_GET(pmic_stpmic1), &dev)) > - return; > + return NULL; > > /* update VDDCORE = BUCK1 */ > if (voltage_mv) > stmpic_buck1_set(dev, voltage_mv); > > - /* Keep vdd on during the reset cycle */ > - pmic_clrsetbits(dev, > - STPMIC1_BUCKS_MRST_CR, > - STPMIC1_MRST_BUCK(STPMIC1_BUCK3), > - STPMIC1_MRST_BUCK(STPMIC1_BUCK3)); > + return dev; > } > diff --git a/board/st/common/stpmic1.h b/board/st/common/stpmic1.h > index b17d6f16338..7a7169d7cea 100644 > --- a/board/st/common/stpmic1.h > +++ b/board/st/common/stpmic1.h > @@ -3,4 +3,4 @@ > * Copyright (C) 2020, STMicroelectronics - All Rights Reserved > */ > > -void stpmic1_init(u32 voltage_mv); > +struct udevice *stpmic1_init(u32 voltage_mv); > diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c > index 747ec7e445a..8b4a529f759 100644 > --- a/board/st/stm32mp1/spl.c > +++ b/board/st/stm32mp1/spl.c > @@ -5,6 +5,8 @@ > > #include <config.h> > #include <common.h> > +#include <power/pmic.h> > +#include <power/stpmic1.h> > #include <asm/arch/sys_proto.h> > #include "../common/stpmic1.h" > > @@ -19,8 +21,15 @@ void board_vddcore_init(u32 voltage_mv) > > int board_early_init_f(void) > { > - if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) > - stpmic1_init(opp_voltage_mv); > + if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) { > + struct udevice *dev = stpmic1_init(opp_voltage_mv); > + > + /* Keep vdd on during the reset cycle */ > + pmic_clrsetbits(dev, > + STPMIC1_BUCKS_MRST_CR, > + STPMIC1_MRST_BUCK(STPMIC1_BUCK3), > + STPMIC1_MRST_BUCK(STPMIC1_BUCK3)); > + } > > return 0; > } Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Thanks Patrick
On 5/25/23 10:08, Patrick DELAUNAY wrote: > Hi Marek, Hello Patrick, sorry for the abysmal delay. > On 5/18/23 00:02, Marek Vasut wrote: >> In case the DHSOM is in suspend state and either reset button is pushed >> or IWDG2 triggers a watchdog reset, then DRAM initialization could fail >> as follows: >> >> " >> RAM: DDR3L 32bits 2x4Gb 533MHz >> DDR invalid size : 0x4, expected 0x40000000 >> DRAM init failed: -22 >> ### ERROR ### Please RESET the board ### >> " >> >> Avoid this failure by not keeping any Buck regulators enabled during >> reset, >> let the SoC and DRAMs power cycle fully. Since the change which keeps >> Buck3 >> VDD enabled during reset is ST specific, move this addition to ST >> specific >> SPL board initialization so that it wouldn't affect the DHSOM . > >> Signed-off-by: Marek Vasut <marex@denx.de> >> --- >> NOTE: This is 2023.07 material >> NOTE: d1a4b09de64 ("board: st: stpmic1: add function stpmic1_init") >> mentions 'keep vdd on during the reset cycle (to avoid issue >> when backup battery is absent)', but there is no further >> description of the 'issue'. Can you please elaborate ? > > > > In the commit message of d1a4b09de643 ("board: st: stpmic1: > > add function stpmic1_init"), I indicated > > - keep vdd on during the reset cycle (to avoid issue when backup battery > is absent) > > > On ST boards we have support of cell coin to allow support of backup > domain, > > but by default this cell are absent and the backup domain is directly > powered > > by VDD (directly connected by resistor). > > > We keep powered this domain to don't loss the backup domain support, > > to avoid to loss the information saved in backup RAM / registers, > > and to be abble to keep DEBUG part powered also. > > > On this ST board, if the VDD is shut down with reset, the backup domain > can't be > > correctly managed for reboot. > > > And to handle correctly power OFF on ST boards with PMIC, we will don't > shut down > > the VDD (full PMIC shut down) but we keep it. > > > So the backup domain is loosed on ST board with STPMIC1 only when the power > > is removed and not for reset or for power off. Thank you for the clarification. I should check suspend/resume on EV1 soon ...
On 5/29/23 03:57, Marek Vasut wrote: Hello again, [...] >> So the backup domain is loosed on ST board with STPMIC1 only when the >> power >> >> is removed and not for reset or for power off. > > Thank you for the clarification. > > I should check suspend/resume on EV1 soon ... We do have this problem on EV1 too I'm afraid: # U-Boot 2f4664f5c3e ("Merge branch '2023-06-14-assorted-fixes'") $ git clean -fqdx ; make stm32mp15_basic_defconfig && make -j$(nproc) $ dd if=u-boot-spl.stm32 of=/dev/sdX1 && dd if=u-boot-spl.stm32 of=/dev/sdX2 && dd if=u-boot.img of=/dev/sdX3 # Linux next 925294c9aa184 ("Add linux-next specific files for 20230615") U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) RAM: DDR3-DDR3L 32bits 533000kHz WDT: Started watchdog@5a002000 with servicing every 1000ms (32s timeout) image entry point: 0xc0100000 U-Boot 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) CPU: STM32MP157FAA Rev.Z Model: STMicroelectronics STM32MP157C eval daughter on eval mother Board: stm32mp1 in basic mode (st,stm32mp157c-ev1) Board: MB1263 Var4.0 Rev.C-03 ... boot as usual into Linux with initramfs for simplicity sake ... $ cat /proc/cmdline console=ttySTM0,115200 no_console_suspend # Suspend the system repeatedly (failure happens after 2-3 wake up cycles) $ while true ; do rtcwake -s 100 -m mem ; done wakeup from "mem" at Sat Jan 1 00:03:11 2000 [ 39.316598] PM: suspend entry (deep) [ 39.318905] Filesystems sync: 0.000 seconds [ 39.324327] Freezing user space processes [ 39.328194] Freezing user space processes completed (elapsed 0.001 seconds) [ 39.334006] OOM killer disabled. [ 39.337158] Freezing remaining freezable tasks [ 39.342777] Freezing remaining freezable tasks completed (elapsed 0.001 seconds) [ 39.426015] Disabling non-boot CPUs ... [ 39.448635] Retrying again to check for CPU kill [ 39.451909] CPU1 killed. U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) RAM: DDR3-DDR3L 32bits 533000kHz DDR invalid size : 0x4, expected 0x40000000 DRAM init failed: -22 ### ERROR ### Please RESET the board ### Press RESET button U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) RAM: DDR3-DDR3L 32bits 533000kHz DDR invalid size : 0x4, expected 0x40000000 DRAM init failed: -22 ### ERROR ### Please RESET the board ###
Hi, On 6/15/23 08:44, Marek Vasut wrote: > On 5/29/23 03:57, Marek Vasut wrote: > > Hello again, > > [...] > >>> So the backup domain is loosed on ST board with STPMIC1 only when >>> the power >>> >>> is removed and not for reset or for power off. >> >> Thank you for the clarification. >> >> I should check suspend/resume on EV1 soon ... > > We do have this problem on EV1 too I'm afraid: > > # U-Boot 2f4664f5c3e ("Merge branch '2023-06-14-assorted-fixes'") > $ git clean -fqdx ; make stm32mp15_basic_defconfig && make -j$(nproc) > $ dd if=u-boot-spl.stm32 of=/dev/sdX1 && dd if=u-boot-spl.stm32 > of=/dev/sdX2 && dd if=u-boot.img of=/dev/sdX3 > > # Linux next 925294c9aa184 ("Add linux-next specific files for 20230615") > > U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) > RAM: DDR3-DDR3L 32bits 533000kHz > WDT: Started watchdog@5a002000 with servicing every 1000ms (32s > timeout) > image entry point: 0xc0100000 > > > U-Boot 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) > > CPU: STM32MP157FAA Rev.Z > Model: STMicroelectronics STM32MP157C eval daughter on eval mother > Board: stm32mp1 in basic mode (st,stm32mp157c-ev1) > Board: MB1263 Var4.0 Rev.C-03 > ... > boot as usual into Linux with initramfs for simplicity sake > ... > $ cat /proc/cmdline > console=ttySTM0,115200 no_console_suspend > > # Suspend the system repeatedly (failure happens after 2-3 wake up > cycles) > $ while true ; do rtcwake -s 100 -m mem ; done > wakeup from "mem" at Sat Jan 1 00:03:11 2000 > [ 39.316598] PM: suspend entry (deep) > [ 39.318905] Filesystems sync: 0.000 seconds > [ 39.324327] Freezing user space processes > [ 39.328194] Freezing user space processes completed (elapsed 0.001 > seconds) > [ 39.334006] OOM killer disabled. > [ 39.337158] Freezing remaining freezable tasks > [ 39.342777] Freezing remaining freezable tasks completed (elapsed > 0.001 seconds) > [ 39.426015] Disabling non-boot CPUs ... > [ 39.448635] Retrying again to check for CPU kill > [ 39.451909] CPU1 killed. > U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) > RAM: DDR3-DDR3L 32bits 533000kHz > DDR invalid size : 0x4, expected 0x40000000 > DRAM init failed: -22 > ### ERROR ### Please RESET the board ### > > Press RESET button > > U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) > RAM: DDR3-DDR3L 32bits 533000kHz > DDR invalid size : 0x4, expected 0x40000000 > DRAM init failed: -22 > ### ERROR ### Please RESET the board ### > > I try it with the latest STMicroelectronics OSS image. I just change in U-Boot config to be aligned the expected SD-Card partionning configs/stm32mp15_basic_defconfig: -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=5 But low power is not supported in this downstream config :-< I got the error: ....... U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3ed-dirty (Jun 16 2023 - 11:37:52 +0200) RAM: DDR3-DDR3L 32bits 533000kHz WDT: Started watchdog@5a002000 with servicing every 1000ms (32s timeout) image entry point: 0xc0100000 U-Boot 2023.07-rc4-00008-g2f4664f5c3ed-dirty (Jun 16 2023 - 11:37:52 +0200) CPU: STM32MP157FAA Rev.Z Model: STMicroelectronics STM32MP157C eval daughter on eval mother Board: stm32mp1 in basic mode (st,stm32mp157c-ev1) Board: MB1263 Var4.0 Rev.C-03 DRAM: 1 GiB Clocks: - MPU : 800 MHz - MCU : 208.878 MHz - AXI : 266.500 MHz - PER : 24 MHz - DDR : 533 MHz Core: 288 devices, 42 uclasses, devicetree: separate WDT: Started watchdog@5a002000 with servicing every 1000ms (32s timeout) NAND: 1024 MiB MMC: STM32 SD/MMC: 0, STM32 SD/MMC: 1 Loading Environment from MMC... Invalid ENV offset in MMC, copy=0 In: serial Out: serial Err: serial Net: eth0: ethernet@5800a000 Hit any key to stop autoboot: 0 .... [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 6.4.0-rc6 (oe-user@oe-host) (arm-ostl-linux-gnueabi-gcc (GCC) 12.2.0, GNU ld (GNU Binutils) 2.40.20230119) #1 SMP PREEMPT Sun Jun 11 21:35:30 UTC 2023 .... root@stm32mp1-disco-oss:~# while true ; do rtcwake -s 100 -m mem ; done rtcwake: unrecognized suspend state 'mem' I check also with downstream (OpenSTLinux V4.0), and I can't reproduced the issue but we are using TF-A / OP-TEE / SCMI to support all the low power modes. And this low power support (in TF-A/ OP-TEE / Linux with SCMI) is not yet up streamed. PS: if you are not able to restart even after a RESET, I assume something is wrong in the PMIC configuration (for example in NVM or in initial regulator configuration) so you have no power cycle on DDR during reset... => something is wrong in PMIC configuration in linux ? before you configure the low power mode in U-Boot and set the DDR in self-refresh in PSCI FW u-boot/arch/arm/mach-stm32mp/psci.c Even if we don't support officially the lower power mode with U-Boot SPL, you can contact directly the STMicroelectonics support on online support : https://community.st.com/s/onlinesupport or post a message on STM32MPUs forum: https://community.st.com/s/topic/0TO0X0000003u2AWAQ/stm32-mpus Regards Patrick
On 6/16/23 15:04, Patrick DELAUNAY wrote: > Hi, Hi, >> [ 39.426015] Disabling non-boot CPUs ... >> [ 39.448635] Retrying again to check for CPU kill >> [ 39.451909] CPU1 killed. >> U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) >> RAM: DDR3-DDR3L 32bits 533000kHz >> DDR invalid size : 0x4, expected 0x40000000 >> DRAM init failed: -22 >> ### ERROR ### Please RESET the board ### >> >> Press RESET button >> >> U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) >> RAM: DDR3-DDR3L 32bits 533000kHz >> DDR invalid size : 0x4, expected 0x40000000 >> DRAM init failed: -22 >> ### ERROR ### Please RESET the board ### >> >> > I try it with the latest STMicroelectronics OSS image. > > I just change in U-Boot config to be aligned the expected SD-Card > partionning > > configs/stm32mp15_basic_defconfig: > > -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=5 > > But low power is not supported in this downstream config :-< Use multi_v7_defconfig or some such ? > I got the error: > > > ....... > U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3ed-dirty (Jun 16 2023 - 11:37:52 > +0200) > RAM: DDR3-DDR3L 32bits 533000kHz > WDT: Started watchdog@5a002000 with servicing every 1000ms (32s timeout) > image entry point: 0xc0100000 > > > U-Boot 2023.07-rc4-00008-g2f4664f5c3ed-dirty (Jun 16 2023 - 11:37:52 +0200) > > CPU: STM32MP157FAA Rev.Z > Model: STMicroelectronics STM32MP157C eval daughter on eval mother > Board: stm32mp1 in basic mode (st,stm32mp157c-ev1) > Board: MB1263 Var4.0 Rev.C-03 > DRAM: 1 GiB > Clocks: > - MPU : 800 MHz > - MCU : 208.878 MHz > - AXI : 266.500 MHz > - PER : 24 MHz > - DDR : 533 MHz > Core: 288 devices, 42 uclasses, devicetree: separate > WDT: Started watchdog@5a002000 with servicing every 1000ms (32s timeout) > NAND: 1024 MiB > MMC: STM32 SD/MMC: 0, STM32 SD/MMC: 1 > Loading Environment from MMC... Invalid ENV offset in MMC, copy=0 > In: serial > Out: serial > Err: serial > Net: eth0: ethernet@5800a000 > Hit any key to stop autoboot: 0 > > .... > [ 0.000000] Booting Linux on physical CPU 0x0 > [ 0.000000] Linux version 6.4.0-rc6 (oe-user@oe-host) > (arm-ostl-linux-gnueabi-gcc (GCC) 12.2.0, GNU ld (GNU Binutils) > 2.40.20230119) #1 SMP PREEMPT Sun Jun 11 21:35:30 UTC 2023 > .... > root@stm32mp1-disco-oss:~# while true ; do rtcwake -s 100 -m mem ; done > rtcwake: unrecognized suspend state 'mem' Please fix your kernel config and enable suspend to mem, I am sure that is not difficult. > I check also with downstream (OpenSTLinux V4.0), This is not relevant to this discussion. > and I can't reproduced the issue but we are using TF-A / OP-TEE / SCMI > to support all the low power modes. > > > And this low power support (in TF-A/ OP-TEE / Linux with SCMI) is not > yet up streamed. > > > PS: if you are not able to restart even after a RESET, > I assume something is wrong in the PMIC configuration > > (for example in NVM or in initial regulator configuration) > > so you have no power cycle on DDR during reset... > > => something is wrong in PMIC configuration in linux ? Possibly, but then it is also something wrong on STM32MP157C EV1, because I can reproduce the failure on EV1 too. I specifically did check this on the EV1. Please fix your kernel config and try again, then you should be able to see it yourself. > before you configure the low power mode in U-Boot and set > the DDR in self-refresh in PSCI FW > > u-boot/arch/arm/mach-stm32mp/psci.c > > > Even if we don't support officially the lower power mode with U-Boot SPL, > > you can contact directly the STMicroelectonics support on online support : This is upstream U-Boot discussion topic, so that discussion should stay on the U-Boot ML.
On 5/18/23 00:02, Marek Vasut wrote: > In case the DHSOM is in suspend state and either reset button is pushed > or IWDG2 triggers a watchdog reset, then DRAM initialization could fail > as follows: > > " > RAM: DDR3L 32bits 2x4Gb 533MHz > DDR invalid size : 0x4, expected 0x40000000 > DRAM init failed: -22 > ### ERROR ### Please RESET the board ### > " > > Avoid this failure by not keeping any Buck regulators enabled during reset, > let the SoC and DRAMs power cycle fully. Since the change which keeps Buck3 > VDD enabled during reset is ST specific, move this addition to ST specific > SPL board initialization so that it wouldn't affect the DHSOM . > > Signed-off-by: Marek Vasut <marex@denx.de> > --- > NOTE: This is 2023.07 material I don't see this one in 2023.07 yet, can you please pick it and send PR? Thanks
On 6/17/23 02:36, Marek Vasut wrote: > On 6/16/23 15:04, Patrick DELAUNAY wrote: >> Hi, > > Hi, > >>> [ 39.426015] Disabling non-boot CPUs ... >>> [ 39.448635] Retrying again to check for CPU kill >>> [ 39.451909] CPU1 killed. >>> U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) >>> RAM: DDR3-DDR3L 32bits 533000kHz >>> DDR invalid size : 0x4, expected 0x40000000 >>> DRAM init failed: -22 >>> ### ERROR ### Please RESET the board ### >>> >>> Press RESET button >>> >>> U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) >>> RAM: DDR3-DDR3L 32bits 533000kHz >>> DDR invalid size : 0x4, expected 0x40000000 >>> DRAM init failed: -22 >>> ### ERROR ### Please RESET the board ### >>> >>> >> I try it with the latest STMicroelectronics OSS image. >> >> I just change in U-Boot config to be aligned the expected SD-Card >> partionning >> >> configs/stm32mp15_basic_defconfig: >> >> -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 >> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=5 >> >> But low power is not supported in this downstream config :-< > > Use multi_v7_defconfig or some such ? > >> I got the error: >> >> >> ....... >> U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3ed-dirty (Jun 16 2023 - >> 11:37:52 +0200) >> RAM: DDR3-DDR3L 32bits 533000kHz >> WDT: Started watchdog@5a002000 with servicing every 1000ms (32s >> timeout) >> image entry point: 0xc0100000 >> >> >> U-Boot 2023.07-rc4-00008-g2f4664f5c3ed-dirty (Jun 16 2023 - 11:37:52 >> +0200) >> >> CPU: STM32MP157FAA Rev.Z >> Model: STMicroelectronics STM32MP157C eval daughter on eval mother >> Board: stm32mp1 in basic mode (st,stm32mp157c-ev1) >> Board: MB1263 Var4.0 Rev.C-03 >> DRAM: 1 GiB >> Clocks: >> - MPU : 800 MHz >> - MCU : 208.878 MHz >> - AXI : 266.500 MHz >> - PER : 24 MHz >> - DDR : 533 MHz >> Core: 288 devices, 42 uclasses, devicetree: separate >> WDT: Started watchdog@5a002000 with servicing every 1000ms (32s >> timeout) >> NAND: 1024 MiB >> MMC: STM32 SD/MMC: 0, STM32 SD/MMC: 1 >> Loading Environment from MMC... Invalid ENV offset in MMC, copy=0 >> In: serial >> Out: serial >> Err: serial >> Net: eth0: ethernet@5800a000 >> Hit any key to stop autoboot: 0 >> >> .... >> [ 0.000000] Booting Linux on physical CPU 0x0 >> [ 0.000000] Linux version 6.4.0-rc6 (oe-user@oe-host) >> (arm-ostl-linux-gnueabi-gcc (GCC) 12.2.0, GNU ld (GNU Binutils) >> 2.40.20230119) #1 SMP PREEMPT Sun Jun 11 21:35:30 UTC 2023 >> .... >> root@stm32mp1-disco-oss:~# while true ; do rtcwake -s 100 -m mem ; done >> rtcwake: unrecognized suspend state 'mem' > > Please fix your kernel config and enable suspend to mem, I am sure that > is not difficult. > >> I check also with downstream (OpenSTLinux V4.0), > > This is not relevant to this discussion. > >> and I can't reproduced the issue but we are using TF-A / OP-TEE / >> SCMI to support all the low power modes. >> >> >> And this low power support (in TF-A/ OP-TEE / Linux with SCMI) is not >> yet up streamed. >> >> >> PS: if you are not able to restart even after a RESET, >> I assume something is wrong in the PMIC configuration >> >> (for example in NVM or in initial regulator configuration) >> >> so you have no power cycle on DDR during reset... >> >> => something is wrong in PMIC configuration in linux ? > > Possibly, but then it is also something wrong on STM32MP157C EV1, > because I can reproduce the failure on EV1 too. I specifically did check > this on the EV1. Please fix your kernel config and try again, then you > should be able to see it yourself. Has there been any news on this defect of EV1 or has this been ignored by ST ?
On 7/4/23 23:55, Marek Vasut wrote: > On 5/18/23 00:02, Marek Vasut wrote: >> In case the DHSOM is in suspend state and either reset button is pushed >> or IWDG2 triggers a watchdog reset, then DRAM initialization could fail >> as follows: >> >> " >> RAM: DDR3L 32bits 2x4Gb 533MHz >> DDR invalid size : 0x4, expected 0x40000000 >> DRAM init failed: -22 >> ### ERROR ### Please RESET the board ### >> " >> >> Avoid this failure by not keeping any Buck regulators enabled during >> reset, >> let the SoC and DRAMs power cycle fully. Since the change which keeps >> Buck3 >> VDD enabled during reset is ST specific, move this addition to ST >> specific >> SPL board initialization so that it wouldn't affect the DHSOM . >> >> Signed-off-by: Marek Vasut <marex@denx.de> >> --- >> NOTE: This is 2023.07 material > > I don't see this one in 2023.07 yet, can you please pick it and send PR? Sadly, this bugfix has not made it into 2023.07, even though the fix was posted a month and half before the actual release.
On 7/10/23 23:43, Marek Vasut wrote: > On 6/17/23 02:36, Marek Vasut wrote: >> On 6/16/23 15:04, Patrick DELAUNAY wrote: >>> Hi, >> >> Hi, >> >>>> [ 39.426015] Disabling non-boot CPUs ... >>>> [ 39.448635] Retrying again to check for CPU kill >>>> [ 39.451909] CPU1 killed. >>>> U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) >>>> RAM: DDR3-DDR3L 32bits 533000kHz >>>> DDR invalid size : 0x4, expected 0x40000000 >>>> DRAM init failed: -22 >>>> ### ERROR ### Please RESET the board ### >>>> >>>> Press RESET button >>>> >>>> U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) >>>> RAM: DDR3-DDR3L 32bits 533000kHz >>>> DDR invalid size : 0x4, expected 0x40000000 >>>> DRAM init failed: -22 >>>> ### ERROR ### Please RESET the board ### >>>> >>>> >>> I try it with the latest STMicroelectronics OSS image. >>> >>> I just change in U-Boot config to be aligned the expected SD-Card partionning >>> >>> configs/stm32mp15_basic_defconfig: >>> >>> -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 >>> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=5 >>> >>> But low power is not supported in this downstream config :-< >> >> Use multi_v7_defconfig or some such ? >> >>> I got the error: >>> >>> >>> ....... >>> U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3ed-dirty (Jun 16 2023 - 11:37:52 +0200) >>> RAM: DDR3-DDR3L 32bits 533000kHz >>> WDT: Started watchdog@5a002000 with servicing every 1000ms (32s timeout) >>> image entry point: 0xc0100000 >>> >>> >>> U-Boot 2023.07-rc4-00008-g2f4664f5c3ed-dirty (Jun 16 2023 - 11:37:52 +0200) >>> >>> CPU: STM32MP157FAA Rev.Z >>> Model: STMicroelectronics STM32MP157C eval daughter on eval mother >>> Board: stm32mp1 in basic mode (st,stm32mp157c-ev1) >>> Board: MB1263 Var4.0 Rev.C-03 >>> DRAM: 1 GiB >>> Clocks: >>> - MPU : 800 MHz >>> - MCU : 208.878 MHz >>> - AXI : 266.500 MHz >>> - PER : 24 MHz >>> - DDR : 533 MHz >>> Core: 288 devices, 42 uclasses, devicetree: separate >>> WDT: Started watchdog@5a002000 with servicing every 1000ms (32s timeout) >>> NAND: 1024 MiB >>> MMC: STM32 SD/MMC: 0, STM32 SD/MMC: 1 >>> Loading Environment from MMC... Invalid ENV offset in MMC, copy=0 >>> In: serial >>> Out: serial >>> Err: serial >>> Net: eth0: ethernet@5800a000 >>> Hit any key to stop autoboot: 0 >>> >>> .... >>> [ 0.000000] Booting Linux on physical CPU 0x0 >>> [ 0.000000] Linux version 6.4.0-rc6 (oe-user@oe-host) (arm-ostl-linux-gnueabi-gcc (GCC) 12.2.0, GNU ld (GNU Binutils) 2.40.20230119) #1 SMP PREEMPT Sun Jun 11 21:35:30 UTC 2023 >>> .... >>> root@stm32mp1-disco-oss:~# while true ; do rtcwake -s 100 -m mem ; done >>> rtcwake: unrecognized suspend state 'mem' >> >> Please fix your kernel config and enable suspend to mem, I am sure that is not difficult. >> >>> I check also with downstream (OpenSTLinux V4.0), >> >> This is not relevant to this discussion. >> >>> and I can't reproduced the issue but we are using TF-A / OP-TEE / SCMI to support all the low power modes. >>> >>> >>> And this low power support (in TF-A/ OP-TEE / Linux with SCMI) is not yet up streamed. >>> >>> >>> PS: if you are not able to restart even after a RESET, >>> I assume something is wrong in the PMIC configuration >>> >>> (for example in NVM or in initial regulator configuration) >>> >>> so you have no power cycle on DDR during reset... >>> >>> => something is wrong in PMIC configuration in linux ? >> >> Possibly, but then it is also something wrong on STM32MP157C EV1, because I can reproduce the failure on EV1 too. I specifically did check this on the EV1. Please fix your kernel config and try again, then you should be able to see it yourself. > > Has there been any news on this defect of EV1 or has this been ignored by ST ? Hi Marek Sorry for the delay, Patch applied on stm32-master Thanks Patrice
On 8/16/23 15:22, Patrice CHOTARD wrote: > > > On 7/10/23 23:43, Marek Vasut wrote: >> On 6/17/23 02:36, Marek Vasut wrote: >>> On 6/16/23 15:04, Patrick DELAUNAY wrote: >>>> Hi, >>> >>> Hi, >>> >>>>> [ 39.426015] Disabling non-boot CPUs ... >>>>> [ 39.448635] Retrying again to check for CPU kill >>>>> [ 39.451909] CPU1 killed. >>>>> U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) >>>>> RAM: DDR3-DDR3L 32bits 533000kHz >>>>> DDR invalid size : 0x4, expected 0x40000000 >>>>> DRAM init failed: -22 >>>>> ### ERROR ### Please RESET the board ### >>>>> >>>>> Press RESET button >>>>> >>>>> U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) >>>>> RAM: DDR3-DDR3L 32bits 533000kHz >>>>> DDR invalid size : 0x4, expected 0x40000000 >>>>> DRAM init failed: -22 >>>>> ### ERROR ### Please RESET the board ### >>>>> >>>>> >>>> I try it with the latest STMicroelectronics OSS image. >>>> >>>> I just change in U-Boot config to be aligned the expected SD-Card partionning >>>> >>>> configs/stm32mp15_basic_defconfig: >>>> >>>> -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 >>>> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=5 >>>> >>>> But low power is not supported in this downstream config :-< >>> >>> Use multi_v7_defconfig or some such ? >>> >>>> I got the error: >>>> >>>> >>>> ....... >>>> U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3ed-dirty (Jun 16 2023 - 11:37:52 +0200) >>>> RAM: DDR3-DDR3L 32bits 533000kHz >>>> WDT: Started watchdog@5a002000 with servicing every 1000ms (32s timeout) >>>> image entry point: 0xc0100000 >>>> >>>> >>>> U-Boot 2023.07-rc4-00008-g2f4664f5c3ed-dirty (Jun 16 2023 - 11:37:52 +0200) >>>> >>>> CPU: STM32MP157FAA Rev.Z >>>> Model: STMicroelectronics STM32MP157C eval daughter on eval mother >>>> Board: stm32mp1 in basic mode (st,stm32mp157c-ev1) >>>> Board: MB1263 Var4.0 Rev.C-03 >>>> DRAM: 1 GiB >>>> Clocks: >>>> - MPU : 800 MHz >>>> - MCU : 208.878 MHz >>>> - AXI : 266.500 MHz >>>> - PER : 24 MHz >>>> - DDR : 533 MHz >>>> Core: 288 devices, 42 uclasses, devicetree: separate >>>> WDT: Started watchdog@5a002000 with servicing every 1000ms (32s timeout) >>>> NAND: 1024 MiB >>>> MMC: STM32 SD/MMC: 0, STM32 SD/MMC: 1 >>>> Loading Environment from MMC... Invalid ENV offset in MMC, copy=0 >>>> In: serial >>>> Out: serial >>>> Err: serial >>>> Net: eth0: ethernet@5800a000 >>>> Hit any key to stop autoboot: 0 >>>> >>>> .... >>>> [ 0.000000] Booting Linux on physical CPU 0x0 >>>> [ 0.000000] Linux version 6.4.0-rc6 (oe-user@oe-host) (arm-ostl-linux-gnueabi-gcc (GCC) 12.2.0, GNU ld (GNU Binutils) 2.40.20230119) #1 SMP PREEMPT Sun Jun 11 21:35:30 UTC 2023 >>>> .... >>>> root@stm32mp1-disco-oss:~# while true ; do rtcwake -s 100 -m mem ; done >>>> rtcwake: unrecognized suspend state 'mem' >>> >>> Please fix your kernel config and enable suspend to mem, I am sure that is not difficult. >>> >>>> I check also with downstream (OpenSTLinux V4.0), >>> >>> This is not relevant to this discussion. >>> >>>> and I can't reproduced the issue but we are using TF-A / OP-TEE / SCMI to support all the low power modes. >>>> >>>> >>>> And this low power support (in TF-A/ OP-TEE / Linux with SCMI) is not yet up streamed. >>>> >>>> >>>> PS: if you are not able to restart even after a RESET, >>>> I assume something is wrong in the PMIC configuration >>>> >>>> (for example in NVM or in initial regulator configuration) >>>> >>>> so you have no power cycle on DDR during reset... >>>> >>>> => something is wrong in PMIC configuration in linux ? >>> >>> Possibly, but then it is also something wrong on STM32MP157C EV1, because I can reproduce the failure on EV1 too. I specifically did check this on the EV1. Please fix your kernel config and try again, then you should be able to see it yourself. >> >> Has there been any news on this defect of EV1 or has this been ignored by ST ? > > Hi Marek Hi, > Sorry for the delay, No worries. What I am more concerned about is -- why is this problem present on EV1 too and how to solve it there ? (and no, "add more unnecessary software to the stack to cover this up" is not the answer) > Patch applied on stm32-master Thank you
On 8/16/23 15:28, Marek Vasut wrote: > On 8/16/23 15:22, Patrice CHOTARD wrote: >> >> >> On 7/10/23 23:43, Marek Vasut wrote: >>> On 6/17/23 02:36, Marek Vasut wrote: >>>> On 6/16/23 15:04, Patrick DELAUNAY wrote: >>>>> Hi, >>>> >>>> Hi, >>>> >>>>>> [ 39.426015] Disabling non-boot CPUs ... >>>>>> [ 39.448635] Retrying again to check for CPU kill >>>>>> [ 39.451909] CPU1 killed. >>>>>> U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 >>>>>> +0200) >>>>>> RAM: DDR3-DDR3L 32bits 533000kHz >>>>>> DDR invalid size : 0x4, expected 0x40000000 >>>>>> DRAM init failed: -22 >>>>>> ### ERROR ### Please RESET the board ### >>>>>> >>>>>> Press RESET button >>>>>> >>>>>> U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3e (Jun 15 2023 - 08:36:52 >>>>>> +0200) >>>>>> RAM: DDR3-DDR3L 32bits 533000kHz >>>>>> DDR invalid size : 0x4, expected 0x40000000 >>>>>> DRAM init failed: -22 >>>>>> ### ERROR ### Please RESET the board ### >>>>>> >>>>>> >>>>> I try it with the latest STMicroelectronics OSS image. >>>>> >>>>> I just change in U-Boot config to be aligned the expected SD-Card >>>>> partionning >>>>> >>>>> configs/stm32mp15_basic_defconfig: >>>>> >>>>> -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 >>>>> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=5 >>>>> >>>>> But low power is not supported in this downstream config :-< >>>> >>>> Use multi_v7_defconfig or some such ? >>>> >>>>> I got the error: >>>>> >>>>> >>>>> ....... >>>>> U-Boot SPL 2023.07-rc4-00008-g2f4664f5c3ed-dirty (Jun 16 2023 - >>>>> 11:37:52 +0200) >>>>> RAM: DDR3-DDR3L 32bits 533000kHz >>>>> WDT: Started watchdog@5a002000 with servicing every 1000ms (32s >>>>> timeout) >>>>> image entry point: 0xc0100000 >>>>> >>>>> >>>>> U-Boot 2023.07-rc4-00008-g2f4664f5c3ed-dirty (Jun 16 2023 - >>>>> 11:37:52 +0200) >>>>> >>>>> CPU: STM32MP157FAA Rev.Z >>>>> Model: STMicroelectronics STM32MP157C eval daughter on eval mother >>>>> Board: stm32mp1 in basic mode (st,stm32mp157c-ev1) >>>>> Board: MB1263 Var4.0 Rev.C-03 >>>>> DRAM: 1 GiB >>>>> Clocks: >>>>> - MPU : 800 MHz >>>>> - MCU : 208.878 MHz >>>>> - AXI : 266.500 MHz >>>>> - PER : 24 MHz >>>>> - DDR : 533 MHz >>>>> Core: 288 devices, 42 uclasses, devicetree: separate >>>>> WDT: Started watchdog@5a002000 with servicing every 1000ms (32s >>>>> timeout) >>>>> NAND: 1024 MiB >>>>> MMC: STM32 SD/MMC: 0, STM32 SD/MMC: 1 >>>>> Loading Environment from MMC... Invalid ENV offset in MMC, copy=0 >>>>> In: serial >>>>> Out: serial >>>>> Err: serial >>>>> Net: eth0: ethernet@5800a000 >>>>> Hit any key to stop autoboot: 0 >>>>> >>>>> .... >>>>> [ 0.000000] Booting Linux on physical CPU 0x0 >>>>> [ 0.000000] Linux version 6.4.0-rc6 (oe-user@oe-host) >>>>> (arm-ostl-linux-gnueabi-gcc (GCC) 12.2.0, GNU ld (GNU Binutils) >>>>> 2.40.20230119) #1 SMP PREEMPT Sun Jun 11 21:35:30 UTC 2023 >>>>> .... >>>>> root@stm32mp1-disco-oss:~# while true ; do rtcwake -s 100 -m mem ; >>>>> done >>>>> rtcwake: unrecognized suspend state 'mem' >>>> >>>> Please fix your kernel config and enable suspend to mem, I am sure >>>> that is not difficult. >>>> >>>>> I check also with downstream (OpenSTLinux V4.0), >>>> >>>> This is not relevant to this discussion. >>>> >>>>> and I can't reproduced the issue but we are using TF-A / OP-TEE / >>>>> SCMI to support all the low power modes. >>>>> >>>>> >>>>> And this low power support (in TF-A/ OP-TEE / Linux with SCMI) is >>>>> not yet up streamed. >>>>> >>>>> >>>>> PS: if you are not able to restart even after a RESET, >>>>> I assume something is wrong in the PMIC configuration >>>>> >>>>> (for example in NVM or in initial regulator configuration) >>>>> >>>>> so you have no power cycle on DDR during reset... >>>>> >>>>> => something is wrong in PMIC configuration in linux ? >>>> >>>> Possibly, but then it is also something wrong on STM32MP157C EV1, >>>> because I can reproduce the failure on EV1 too. I specifically did >>>> check this on the EV1. Please fix your kernel config and try again, >>>> then you should be able to see it yourself. >>> >>> Has there been any news on this defect of EV1 or has this been >>> ignored by ST ? >> >> Hi Marek > > Hi, > >> Sorry for the delay, > > No worries. > > What I am more concerned about is -- why is this problem present on EV1 > too and how to solve it there ? (and no, "add more unnecessary software > to the stack to cover this up" is not the answer) I ran into this defect again, it seems the EV1 problem is ignored by ST, or are there any news ?
diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c index d52dce4f657..969ad484864 100644 --- a/board/st/common/stpmic1.c +++ b/board/st/common/stpmic1.c @@ -185,21 +185,17 @@ static int stmpic_buck1_set(struct udevice *dev, u32 voltage_mv) } /* early init of PMIC */ -void stpmic1_init(u32 voltage_mv) +struct udevice *stpmic1_init(u32 voltage_mv) { struct udevice *dev; if (uclass_get_device_by_driver(UCLASS_PMIC, DM_DRIVER_GET(pmic_stpmic1), &dev)) - return; + return NULL; /* update VDDCORE = BUCK1 */ if (voltage_mv) stmpic_buck1_set(dev, voltage_mv); - /* Keep vdd on during the reset cycle */ - pmic_clrsetbits(dev, - STPMIC1_BUCKS_MRST_CR, - STPMIC1_MRST_BUCK(STPMIC1_BUCK3), - STPMIC1_MRST_BUCK(STPMIC1_BUCK3)); + return dev; } diff --git a/board/st/common/stpmic1.h b/board/st/common/stpmic1.h index b17d6f16338..7a7169d7cea 100644 --- a/board/st/common/stpmic1.h +++ b/board/st/common/stpmic1.h @@ -3,4 +3,4 @@ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved */ -void stpmic1_init(u32 voltage_mv); +struct udevice *stpmic1_init(u32 voltage_mv); diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c index 747ec7e445a..8b4a529f759 100644 --- a/board/st/stm32mp1/spl.c +++ b/board/st/stm32mp1/spl.c @@ -5,6 +5,8 @@ #include <config.h> #include <common.h> +#include <power/pmic.h> +#include <power/stpmic1.h> #include <asm/arch/sys_proto.h> #include "../common/stpmic1.h" @@ -19,8 +21,15 @@ void board_vddcore_init(u32 voltage_mv) int board_early_init_f(void) { - if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) - stpmic1_init(opp_voltage_mv); + if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) { + struct udevice *dev = stpmic1_init(opp_voltage_mv); + + /* Keep vdd on during the reset cycle */ + pmic_clrsetbits(dev, + STPMIC1_BUCKS_MRST_CR, + STPMIC1_MRST_BUCK(STPMIC1_BUCK3), + STPMIC1_MRST_BUCK(STPMIC1_BUCK3)); + } return 0; }
In case the DHSOM is in suspend state and either reset button is pushed or IWDG2 triggers a watchdog reset, then DRAM initialization could fail as follows: " RAM: DDR3L 32bits 2x4Gb 533MHz DDR invalid size : 0x4, expected 0x40000000 DRAM init failed: -22 ### ERROR ### Please RESET the board ### " Avoid this failure by not keeping any Buck regulators enabled during reset, let the SoC and DRAMs power cycle fully. Since the change which keeps Buck3 VDD enabled during reset is ST specific, move this addition to ST specific SPL board initialization so that it wouldn't affect the DHSOM . Signed-off-by: Marek Vasut <marex@denx.de> --- NOTE: This is 2023.07 material NOTE: d1a4b09de64 ("board: st: stpmic1: add function stpmic1_init") mentions 'keep vdd on during the reset cycle (to avoid issue when backup battery is absent)', but there is no further description of the 'issue'. Can you please elaborate ? --- Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com --- board/st/common/stpmic1.c | 10 +++------- board/st/common/stpmic1.h | 2 +- board/st/stm32mp1/spl.c | 13 +++++++++++-- 3 files changed, 15 insertions(+), 10 deletions(-)