diff mbox series

[v2,u-boot] pci: fsl: Do not access PCI BAR0 register of PCIe Root Port

Message ID 20230502175357.18072-1-pali@kernel.org
State Accepted
Commit 0d734df4a459f01fdf1e62512fb28b28022cb6a9
Delegated to: Tom Rini
Headers show
Series [v2,u-boot] pci: fsl: Do not access PCI BAR0 register of PCIe Root Port | expand

Commit Message

Pali Rohár May 2, 2023, 5:53 p.m. UTC 
Freescale PCIe Root Port has PEXCSRBAR register at position of PCI BAR0.
PCIe Root Port does not have any PCIe memory, so returns zero when trying
to read from PCIe Root Port BAR0 and ignore any writes.

Signed-off-by: Pali Rohár <pali@kernel.org>
---
 drivers/pci/pcie_fsl.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

Comments

Tom Rini May 4, 2023, 3:52 p.m. UTC | #1 
On Tue, May 02, 2023 at 07:53:57PM +0200, Pali Rohár wrote:

> Freescale PCIe Root Port has PEXCSRBAR register at position of PCI BAR0.
> PCIe Root Port does not have any PCIe memory, so returns zero when trying
> to read from PCIe Root Port BAR0 and ignore any writes.
> 
> Signed-off-by: Pali Rohár <pali@kernel.org>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 4600652f2b1b..8d89a1e5919c 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -58,6 +58,14 @@  static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
 		return 0;
 	}
 
+	/* Skip Freescale PCIe controller's PEXCSRBAR register */
+	if (PCI_BUS(bdf) - dev_seq(bus) == 0 &&
+	    PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+	    (offset & ~3) == PCI_BASE_ADDRESS_0) {
+		*valuep = 0;
+		return 0;
+	}
+
 	val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus),
 				    PCI_DEV(bdf), PCI_FUNC(bdf),
 				    offset);
@@ -95,6 +103,12 @@  static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
 	if (fsl_pcie_addr_valid(pcie, bdf))
 		return 0;
 
+	/* Skip Freescale PCIe controller's PEXCSRBAR register */
+	if (PCI_BUS(bdf) - dev_seq(bus) == 0 &&
+	    PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+	    (offset & ~3) == PCI_BASE_ADDRESS_0)
+		return 0;
+
 	val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus),
 				    PCI_DEV(bdf), PCI_FUNC(bdf),
 				    offset);