diff mbox series

[v1,3/5] arm: socfpga: soc64: Add F2SDRAM sideband manager base address for SOC64

Message ID 20230423181124.28077-4-sin.hui.kho@intel.com
State Needs Review / ACK, archived
Delegated to: Marek Vasut
Headers show
Series Add new DDR driver support for Agilex7 | expand

Commit Message

sin.hui.kho@intel.com April 23, 2023, 6:11 p.m. UTC 
From: Sin Hui Kho <sin.hui.kho@intel.com>

F2SDRAM sideband manager in MPFE is used in DDR driver to configure the
data traffic path.

Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
---
 arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
index eecbb037f5..cee7d482c8 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
@@ -17,6 +17,7 @@ 
 #else
 #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS		0xf8020100
 #endif
+#define SOCFPGA_F2SDRAM_MGR_ADDRESS		0xf8024000
 #define SOCFPGA_SMMU_ADDRESS			0xfa000000
 #define SOCFPGA_MAILBOX_ADDRESS			0xffa30000
 #define SOCFPGA_UART0_ADDRESS			0xffc02000