@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2019-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2019-2023 Intel Corporation <www.intel.com>
*/
#ifndef _SYSTEM_MANAGER_SOC64_H_
@@ -102,6 +102,23 @@ void populate_sysmgr_pinmux(void);
#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30)
#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28))
#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28
+/*
+ * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD8
+ * Bit[31] reserved for FSBL to check DDR DBE is triggered (set by SDM to "1") ?
+ *
+ * Bit[30] reserved for FSBL to update the DDR init progress
+ * 1 - means in progress, 0 - haven't started / DDR is up running.
+ *
+ * Bit[29] reserved for FSBL to check OCRAM DBE is triggered (set by SDM to "1")
+ *
+ * Bit[17:1] - Setting by Linux EDAC.
+ * Bit[1](ECC_OCRAM), Bit[16](ECC_DDR0), Bit[17](ECC_DDR1)
+ */
+#define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK BIT(31)
+#define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK BIT(30)
+#define ALT_SYSMGR_SCRATCH_REG_8_OCRAM_DBE_MASK BIT(29)
+#define ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_MASK GENMASK(28, 27)
+#define ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_SHIFT 27
#define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC