diff mbox series

[v4] ARM: dts: imx7d-sdb-u-boot: Fix usdhc1 UHS operation

Message ID 20230412124104.2430888-1-festevam@gmail.com
State Accepted
Commit 0aea5dda292889c3e87e38ad003e53e508b7fc08
Delegated to: Stefano Babic
Headers show
Series [v4] ARM: dts: imx7d-sdb-u-boot: Fix usdhc1 UHS operation | expand

Commit Message

Fabio Estevam April 12, 2023, 12:41 p.m. UTC 
From: Fabio Estevam <festevam@denx.de>

Commit 1a7904fdfa7d ("mmc: fsl_esdhc_imx: Use esdhc_soc_data
flags to set host caps") exposed the following SD card error:

U-Boot 2023.04-00652-g487e42f7bc5e (Apr 05 2023 - 22:14:21 -0300)

CPU:   Freescale i.MX7D rev1.0 1000 MHz (running at 792 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 35C
Reset cause: POR
Model: Freescale i.MX7 SabreSD Board
Board: i.MX7D SABRESD in non-secure mode
DRAM:  1 GiB
Core:  100 devices, 19 uclasses, devicetree: separate
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... Card did not respond to voltage
select! : -110
*** Warning - No block device, using default environment

The reason of the problem, as explained by Ye Li:

"When UHS is enabled in defconfig, the usdhc1 node in imx7d-sdb.dts does
not configure pad for VSELECT, also the data pad should be set to
100Mhz/200Mhz pin states."

Apply these changes into u-boot.dtsi for now. When these changes
reach the Linux mainline imx7d-sdb, they can be dropped from u-boot.dtsi.

This fixes UHS mode on the imx7d-sdb board.

Suggested-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
Changes since v3:
- Fixed a typo on the pinctrl_usdhc1 node.

 arch/arm/dts/imx7d-sdb-u-boot.dtsi | 51 ++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

Comments

Peng Fan (OSS) April 13, 2023, 6:51 a.m. UTC | #1 
On 4/12/2023 8:41 PM, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@denx.de>
> 
> Commit 1a7904fdfa7d ("mmc: fsl_esdhc_imx: Use esdhc_soc_data
> flags to set host caps") exposed the following SD card error:
> 
> U-Boot 2023.04-00652-g487e42f7bc5e (Apr 05 2023 - 22:14:21 -0300)
> 
> CPU:   Freescale i.MX7D rev1.0 1000 MHz (running at 792 MHz)
> CPU:   Commercial temperature grade (0C to 95C) at 35C
> Reset cause: POR
> Model: Freescale i.MX7 SabreSD Board
> Board: i.MX7D SABRESD in non-secure mode
> DRAM:  1 GiB
> Core:  100 devices, 19 uclasses, devicetree: separate
> PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x10
> MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
> Loading Environment from MMC... Card did not respond to voltage
> select! : -110
> *** Warning - No block device, using default environment
> 
> The reason of the problem, as explained by Ye Li:
> 
> "When UHS is enabled in defconfig, the usdhc1 node in imx7d-sdb.dts does
> not configure pad for VSELECT, also the data pad should be set to
> 100Mhz/200Mhz pin states."
> 
> Apply these changes into u-boot.dtsi for now. When these changes
> reach the Linux mainline imx7d-sdb, they can be dropped from u-boot.dtsi.
> 
> This fixes UHS mode on the imx7d-sdb board.
> 
> Suggested-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Fabio Estevam <festevam@denx.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
> Changes since v3:
> - Fixed a typo on the pinctrl_usdhc1 node.
> 
>   arch/arm/dts/imx7d-sdb-u-boot.dtsi | 51 ++++++++++++++++++++++++++++++
>   1 file changed, 51 insertions(+)
> 
> diff --git a/arch/arm/dts/imx7d-sdb-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-u-boot.dtsi
> index b78358fa1397..913127b5e3c2 100644
> --- a/arch/arm/dts/imx7d-sdb-u-boot.dtsi
> +++ b/arch/arm/dts/imx7d-sdb-u-boot.dtsi
> @@ -5,3 +5,54 @@
>   &usbotg1 {
>   	dr_mode = "peripheral";
>   };
> +
> +&usdhc1 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
> +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
> +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
> +};
> +
> +&pinctrl_usdhc1 {
> +		fsl,pins = <
> +			MX7D_PAD_SD1_CMD__SD1_CMD		0x59
> +			MX7D_PAD_SD1_CLK__SD1_CLK		0x19
> +			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
> +			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
> +			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
> +			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
> +		>;
> +};
> +
> +&iomuxc {
> +	pinctrl_usdhc1_gpio: usdhc1gpiogrp {
> +		fsl,pins = <
> +			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x59 /* CD */
> +			MX7D_PAD_SD1_WP__GPIO5_IO1		0x59 /* WP */
> +			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x59 /* vmmc */
> +			MX7D_PAD_GPIO1_IO08__SD1_VSELECT	0x59 /* VSELECT */
> +		>;
> +	};
> +
> +	pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {
> +		fsl,pins = <
> +			MX7D_PAD_SD1_CMD__SD1_CMD		0x5a
> +			MX7D_PAD_SD1_CLK__SD1_CLK		0x1a
> +			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a
> +			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a
> +			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a
> +			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a
> +		>;
> +	};
> +
> +	pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {
> +		fsl,pins = <
> +			MX7D_PAD_SD1_CMD__SD1_CMD		0x5b
> +			MX7D_PAD_SD1_CLK__SD1_CLK		0x1b
> +			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b
> +			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b
> +			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b
> +			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b
> +		>;
> +	};
> +};
Stefano Babic May 21, 2023, 4:55 p.m. UTC | #2 
> From: Fabio Estevam <festevam@denx.de>
> Commit 1a7904fdfa7d ("mmc: fsl_esdhc_imx: Use esdhc_soc_data
> flags to set host caps") exposed the following SD card error:
> U-Boot 2023.04-00652-g487e42f7bc5e (Apr 05 2023 - 22:14:21 -0300)
> CPU:   Freescale i.MX7D rev1.0 1000 MHz (running at 792 MHz)
> CPU:   Commercial temperature grade (0C to 95C) at 35C
> Reset cause: POR
> Model: Freescale i.MX7 SabreSD Board
> Board: i.MX7D SABRESD in non-secure mode
> DRAM:  1 GiB
> Core:  100 devices, 19 uclasses, devicetree: separate
> PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x10
> MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
> Loading Environment from MMC... Card did not respond to voltage
> select! : -110
> *** Warning - No block device, using default environment
> The reason of the problem, as explained by Ye Li:
> "When UHS is enabled in defconfig, the usdhc1 node in imx7d-sdb.dts does
> not configure pad for VSELECT, also the data pad should be set to
> 100Mhz/200Mhz pin states."
> Apply these changes into u-boot.dtsi for now. When these changes
> reach the Linux mainline imx7d-sdb, they can be dropped from u-boot.dtsi.
> This fixes UHS mode on the imx7d-sdb board.
> Suggested-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Fabio Estevam <festevam@denx.de>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic
diff mbox series

Patch

diff --git a/arch/arm/dts/imx7d-sdb-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-u-boot.dtsi
index b78358fa1397..913127b5e3c2 100644
--- a/arch/arm/dts/imx7d-sdb-u-boot.dtsi
+++ b/arch/arm/dts/imx7d-sdb-u-boot.dtsi
@@ -5,3 +5,54 @@ 
 &usbotg1 {
 	dr_mode = "peripheral";
 };
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
+};
+
+&pinctrl_usdhc1 {
+		fsl,pins = <
+			MX7D_PAD_SD1_CMD__SD1_CMD		0x59
+			MX7D_PAD_SD1_CLK__SD1_CLK		0x19
+			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
+			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
+			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
+			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
+		>;
+};
+
+&iomuxc {
+	pinctrl_usdhc1_gpio: usdhc1gpiogrp {
+		fsl,pins = <
+			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x59 /* CD */
+			MX7D_PAD_SD1_WP__GPIO5_IO1		0x59 /* WP */
+			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x59 /* vmmc */
+			MX7D_PAD_GPIO1_IO08__SD1_VSELECT	0x59 /* VSELECT */
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {
+		fsl,pins = <
+			MX7D_PAD_SD1_CMD__SD1_CMD		0x5a
+			MX7D_PAD_SD1_CLK__SD1_CLK		0x1a
+			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a
+			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a
+			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a
+			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {
+		fsl,pins = <
+			MX7D_PAD_SD1_CMD__SD1_CMD		0x5b
+			MX7D_PAD_SD1_CLK__SD1_CLK		0x1b
+			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b
+			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b
+			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b
+			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b
+		>;
+	};
+};