diff mbox series

[v2,4/5] board: verdin-imx8mp: compact slight different lpddr4 configuration

Message ID 20230403120157.123621-5-marcel@ziswiler.com
State Accepted
Commit 0e897621b44931053aa7fd547f2fc50bd46e4a90
Delegated to: Stefano Babic
Headers show
Series board: verdin-imx8mp: ddr updates | expand

Commit Message

Marcel Ziswiler April 3, 2023, 12:01 p.m. UTC 
From: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>

Deduplicate similar DDRC configurations and LPDDR4 training patterns
by patching a single configuration.

The aim is to reduce the SPL memory footprint and simplify maintenance
of lpddr4_timing.c

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---

(no changes since v1)

 board/toradex/verdin-imx8mp/lpddr4_timing.c | 380 ++++----------------
 board/toradex/verdin-imx8mp/lpddr4_timing.h |  11 +
 board/toradex/verdin-imx8mp/spl.c           |   6 +-
 3 files changed, 75 insertions(+), 322 deletions(-)
 create mode 100644 board/toradex/verdin-imx8mp/lpddr4_timing.h

Comments

Stefano Babic April 4, 2023, 10:19 a.m. UTC | #1 
> From: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
> Deduplicate similar DDRC configurations and LPDDR4 training patterns
> by patching a single configuration.
> The aim is to reduce the SPL memory footprint and simplify maintenance
> of lpddr4_timing.c
> Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Applied to u-boot-imx, next, thanks !

Best regards,
Stefano Babic
diff mbox series

Patch

diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.c b/board/toradex/verdin-imx8mp/lpddr4_timing.c
index 4f0bbe6ce16..29ea31e1461 100644
--- a/board/toradex/verdin-imx8mp/lpddr4_timing.c
+++ b/board/toradex/verdin-imx8mp/lpddr4_timing.c
@@ -13,6 +13,33 @@ 
 
 #include <linux/kernel.h>
 #include <asm/arch/ddr.h>
+#include "lpddr4_timing.h"
+
+struct dram_cfg_param ddr_ddrc_cfg_single_rank_patch[] = {
+	{ 0x3d400000, 0xa1080020},
+	{ 0x3d400200, 0x1f},
+	{ 0x3d40021c, 0xf07}
+};
+
+struct dram_cfg_param ddr_fsp0_cfg_single_rank_patch[] = {
+	{ 0x54012, 0x110},
+	{ 0x5402c, 0x1}
+};
+
+struct dram_cfg_param ddr_fsp1_cfg_single_rank_patch[] = {
+	{ 0x54012, 0x110},
+	{ 0x5402c, 0x1}
+};
+
+struct dram_cfg_param ddr_fsp2_cfg_single_rank_patch[] = {
+	{ 0x54012, 0x110},
+	{ 0x5402c, 0x1}
+};
+
+struct dram_cfg_param ddr_fsp0_2d_cfg_single_rank_patch[] = {
+	{ 0x54012, 0x110},
+	{ 0x5402c, 0x1}
+};
 
 struct dram_cfg_param ddr_ddrc_cfg[] = {
 	/** Initialize DDRC registers **/
@@ -1835,311 +1862,7 @@  struct dram_fsp_msg ddr_dram_fsp_msg[] = {
 	},
 };
 
-struct dram_cfg_param ddr_ddrc_cfg2[] = {
-	/** Initialize DDRC registers **/
-	{ 0x3d400304, 0x1 },
-	{ 0x3d400030, 0x1 },
-	{ 0x3d400000, 0xa1080020 },
-	{ 0x3d400020, 0x1303 },
-	{ 0x3d400024, 0x1e84800 },
-	{ 0x3d400064, 0x7a017c },
-	{ 0x3d400070, 0x7027f90 },
-	{ 0x3d400074, 0x790 },
-	{ 0x3d4000d0, 0xc00307a3 },
-	{ 0x3d4000d4, 0xc50000 },
-	{ 0x3d4000dc, 0xf4003f },
-	{ 0x3d4000e0, 0x330000 },
-	{ 0x3d4000e8, 0x660048 },
-	{ 0x3d4000ec, 0x160048 },
-	{ 0x3d400100, 0x2028222a },
-	{ 0x3d400104, 0x8083f },
-	{ 0x3d40010c, 0xe0e000 },
-	{ 0x3d400110, 0x12040a12 },
-	{ 0x3d400114, 0x2050f0f },
-	{ 0x3d400118, 0x1010009 },
-	{ 0x3d40011c, 0x502 },
-	{ 0x3d400130, 0x20800 },
-	{ 0x3d400134, 0xe100002 },
-	{ 0x3d400138, 0x184 },
-	{ 0x3d400144, 0xc80064 },
-	{ 0x3d400180, 0x3e8001e },
-	{ 0x3d400184, 0x3207a12 },
-	{ 0x3d400188, 0x0 },
-	{ 0x3d400190, 0x49f820e },
-	{ 0x3d400194, 0x80303 },
-	{ 0x3d4001b4, 0x1f0e },
-	{ 0x3d4001a0, 0xe0400018 },
-	{ 0x3d4001a4, 0xdf00e4 },
-	{ 0x3d4001a8, 0x80000000 },
-	{ 0x3d4001b0, 0x11 },
-	{ 0x3d4001c0, 0x1 },
-	{ 0x3d4001c4, 0x1 },
-	{ 0x3d4000f4, 0x799 },
-	{ 0x3d400108, 0x9121b1c },
-	{ 0x3d400200, 0x1f },
-	{ 0x3d400208, 0x0 },
-	{ 0x3d40020c, 0x0 },
-	{ 0x3d400210, 0x1f1f },
-	{ 0x3d400204, 0x80808 },
-	{ 0x3d400214, 0x7070707 },
-	{ 0x3d400218, 0x7070707 },
-	{ 0x3d40021c, 0xf07 },
-	{ 0x3d400250, 0x1705 },
-	{ 0x3d400254, 0x2c },
-	{ 0x3d40025c, 0x4000030 },
-	{ 0x3d400264, 0x900093e7 },
-	{ 0x3d40026c, 0x2005574 },
-	{ 0x3d400400, 0x111 },
-	{ 0x3d400404, 0x72ff },
-	{ 0x3d400408, 0x72ff },
-	{ 0x3d400494, 0x2100e07 },
-	{ 0x3d400498, 0x620096 },
-	{ 0x3d40049c, 0x1100e07 },
-	{ 0x3d4004a0, 0xc8012c },
-	{ 0x3d402020, 0x1001 },
-	{ 0x3d402024, 0x30d400 },
-	{ 0x3d402050, 0x20d000 },
-	{ 0x3d402064, 0xc0026 },
-	{ 0x3d4020dc, 0x840000 },
-	{ 0x3d4020e0, 0x330000 },
-	{ 0x3d4020e8, 0x660048 },
-	{ 0x3d4020ec, 0x160048 },
-	{ 0x3d402100, 0xa040305 },
-	{ 0x3d402104, 0x30407 },
-	{ 0x3d402108, 0x203060b },
-	{ 0x3d40210c, 0x505000 },
-	{ 0x3d402110, 0x2040202 },
-	{ 0x3d402114, 0x2030202 },
-	{ 0x3d402118, 0x1010004 },
-	{ 0x3d40211c, 0x302 },
-	{ 0x3d402130, 0x20300 },
-	{ 0x3d402134, 0xa100002 },
-	{ 0x3d402138, 0x27 },
-	{ 0x3d402144, 0x14000a },
-	{ 0x3d402180, 0x640004 },
-	{ 0x3d402190, 0x3818200 },
-	{ 0x3d402194, 0x80303 },
-	{ 0x3d4021b4, 0x100 },
-	{ 0x3d4020f4, 0x599 },
-	{ 0x3d403020, 0x1001 },
-	{ 0x3d403024, 0xc3500 },
-	{ 0x3d403050, 0x20d000 },
-	{ 0x3d403064, 0x3000a },
-	{ 0x3d4030dc, 0x840000 },
-	{ 0x3d4030e0, 0x330000 },
-	{ 0x3d4030e8, 0x660048 },
-	{ 0x3d4030ec, 0x160048 },
-	{ 0x3d403100, 0xa010102 },
-	{ 0x3d403104, 0x30404 },
-	{ 0x3d403108, 0x203060b },
-	{ 0x3d40310c, 0x505000 },
-	{ 0x3d403110, 0x2040202 },
-	{ 0x3d403114, 0x2030202 },
-	{ 0x3d403118, 0x1010004 },
-	{ 0x3d40311c, 0x302 },
-	{ 0x3d403130, 0x20300 },
-	{ 0x3d403134, 0xa100002 },
-	{ 0x3d403138, 0xa },
-	{ 0x3d403144, 0x50003 },
-	{ 0x3d403180, 0x190004 },
-	{ 0x3d403190, 0x3818200 },
-	{ 0x3d403194, 0x80303 },
-	{ 0x3d4031b4, 0x100 },
-	{ 0x3d4030f4, 0x599 },
-	{ 0x3d400028, 0x0 },
-};
-
-/* P0 message block parameter for training firmware */
-struct dram_cfg_param ddr_fsp0_cfg2[] = {
-	{ 0xd0000, 0x0 },
-	{ 0x54003, 0xfa0 },
-	{ 0x54004, 0x2 },
-	{ 0x54005, 0x2228 },
-	{ 0x54006, 0x14 },
-	{ 0x54008, 0x131f },
-	{ 0x54009, 0xc8 },
-	{ 0x5400b, 0x2 },
-	{ 0x5400f, 0x100 },
-	{ 0x54012, 0x110 },
-	{ 0x54019, 0x3ff4 },
-	{ 0x5401a, 0x33 },
-	{ 0x5401b, 0x4866 },
-	{ 0x5401c, 0x4800 },
-	{ 0x5401e, 0x16 },
-	{ 0x5401f, 0x3ff4 },
-	{ 0x54020, 0x33 },
-	{ 0x54021, 0x4866 },
-	{ 0x54022, 0x4800 },
-	{ 0x54024, 0x16 },
-	{ 0x5402b, 0x1000 },
-	{ 0x5402c, 0x1 },
-	{ 0x54032, 0xf400 },
-	{ 0x54033, 0x333f },
-	{ 0x54034, 0x6600 },
-	{ 0x54035, 0x48 },
-	{ 0x54036, 0x48 },
-	{ 0x54037, 0x1600 },
-	{ 0x54038, 0xf400 },
-	{ 0x54039, 0x333f },
-	{ 0x5403a, 0x6600 },
-	{ 0x5403b, 0x48 },
-	{ 0x5403c, 0x48 },
-	{ 0x5403d, 0x1600 },
-	{ 0xd0000, 0x1 },
-};
-
-/* P1 message block parameter for training firmware */
-struct dram_cfg_param ddr_fsp1_cfg2[] = {
-	{ 0xd0000, 0x0 },
-	{ 0x54002, 0x101 },
-	{ 0x54003, 0x190 },
-	{ 0x54004, 0x2 },
-	{ 0x54005, 0x2228 },
-	{ 0x54006, 0x14 },
-	{ 0x54008, 0x121f },
-	{ 0x54009, 0xc8 },
-	{ 0x5400b, 0x2 },
-	{ 0x5400f, 0x100 },
-	{ 0x54012, 0x110 },
-	{ 0x54019, 0x84 },
-	{ 0x5401a, 0x33 },
-	{ 0x5401b, 0x4866 },
-	{ 0x5401c, 0x4800 },
-	{ 0x5401e, 0x16 },
-	{ 0x5401f, 0x84 },
-	{ 0x54020, 0x33 },
-	{ 0x54021, 0x4866 },
-	{ 0x54022, 0x4800 },
-	{ 0x54024, 0x16 },
-	{ 0x5402b, 0x1000 },
-	{ 0x5402c, 0x1 },
-	{ 0x54032, 0x8400 },
-	{ 0x54033, 0x3300 },
-	{ 0x54034, 0x6600 },
-	{ 0x54035, 0x48 },
-	{ 0x54036, 0x48 },
-	{ 0x54037, 0x1600 },
-	{ 0x54038, 0x8400 },
-	{ 0x54039, 0x3300 },
-	{ 0x5403a, 0x6600 },
-	{ 0x5403b, 0x48 },
-	{ 0x5403c, 0x48 },
-	{ 0x5403d, 0x1600 },
-	{ 0xd0000, 0x1 },
-};
-
-/* P2 message block parameter for training firmware */
-struct dram_cfg_param ddr_fsp2_cfg2[] = {
-	{ 0xd0000, 0x0 },
-	{ 0x54002, 0x102 },
-	{ 0x54003, 0x64 },
-	{ 0x54004, 0x2 },
-	{ 0x54005, 0x2228 },
-	{ 0x54006, 0x14 },
-	{ 0x54008, 0x121f },
-	{ 0x54009, 0xc8 },
-	{ 0x5400b, 0x2 },
-	{ 0x5400f, 0x100 },
-	{ 0x54012, 0x110 },
-	{ 0x54019, 0x84 },
-	{ 0x5401a, 0x33 },
-	{ 0x5401b, 0x4866 },
-	{ 0x5401c, 0x4800 },
-	{ 0x5401e, 0x16 },
-	{ 0x5401f, 0x84 },
-	{ 0x54020, 0x33 },
-	{ 0x54021, 0x4866 },
-	{ 0x54022, 0x4800 },
-	{ 0x54024, 0x16 },
-	{ 0x5402b, 0x1000 },
-	{ 0x5402c, 0x1 },
-	{ 0x54032, 0x8400 },
-	{ 0x54033, 0x3300 },
-	{ 0x54034, 0x6600 },
-	{ 0x54035, 0x48 },
-	{ 0x54036, 0x48 },
-	{ 0x54037, 0x1600 },
-	{ 0x54038, 0x8400 },
-	{ 0x54039, 0x3300 },
-	{ 0x5403a, 0x6600 },
-	{ 0x5403b, 0x48 },
-	{ 0x5403c, 0x48 },
-	{ 0x5403d, 0x1600 },
-	{ 0xd0000, 0x1 },
-};
-
-/* P0 2D message block parameter for training firmware */
-struct dram_cfg_param ddr_fsp0_2d_cfg2[] = {
-	{ 0xd0000, 0x0 },
-	{ 0x54003, 0xfa0 },
-	{ 0x54004, 0x2 },
-	{ 0x54005, 0x2228 },
-	{ 0x54006, 0x14 },
-	{ 0x54008, 0x61 },
-	{ 0x54009, 0xc8 },
-	{ 0x5400b, 0x2 },
-	{ 0x5400f, 0x100 },
-	{ 0x54010, 0x1f7f },
-	{ 0x54012, 0x110 },
-	{ 0x54019, 0x3ff4 },
-	{ 0x5401a, 0x33 },
-	{ 0x5401b, 0x4866 },
-	{ 0x5401c, 0x4800 },
-	{ 0x5401e, 0x16 },
-	{ 0x5401f, 0x3ff4 },
-	{ 0x54020, 0x33 },
-	{ 0x54021, 0x4866 },
-	{ 0x54022, 0x4800 },
-	{ 0x54024, 0x16 },
-	{ 0x5402b, 0x1000 },
-	{ 0x5402c, 0x1 },
-	{ 0x54032, 0xf400 },
-	{ 0x54033, 0x333f },
-	{ 0x54034, 0x6600 },
-	{ 0x54035, 0x48 },
-	{ 0x54036, 0x48 },
-	{ 0x54037, 0x1600 },
-	{ 0x54038, 0xf400 },
-	{ 0x54039, 0x333f },
-	{ 0x5403a, 0x6600 },
-	{ 0x5403b, 0x48 },
-	{ 0x5403c, 0x48 },
-	{ 0x5403d, 0x1600 },
-	{ 0xd0000, 0x1 },
-};
-
-struct dram_fsp_msg ddr_dram_fsp_msg2[] = {
-	{
-		/* P0 4000mts 1D */
-		.drate = 4000,
-		.fw_type = FW_1D_IMAGE,
-		.fsp_cfg = ddr_fsp0_cfg2,
-		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg2),
-	},
-	{
-		/* P1 400mts 1D */
-		.drate = 400,
-		.fw_type = FW_1D_IMAGE,
-		.fsp_cfg = ddr_fsp1_cfg2,
-		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg2),
-	},
-	{
-		/* P2 100mts 1D */
-		.drate = 100,
-		.fw_type = FW_1D_IMAGE,
-		.fsp_cfg = ddr_fsp2_cfg2,
-		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg2),
-	},
-	{
-		/* P0 4000mts 2D */
-		.drate = 4000,
-		.fw_type = FW_2D_IMAGE,
-		.fsp_cfg = ddr_fsp0_2d_cfg2,
-		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg2),
-	},
-};
-
-/* quad die, dual rank aka 8 GB DDR timing config params */
+/* ddr timing config params */
 struct dram_timing_info dram_timing = {
 	.ddrc_cfg = ddr_ddrc_cfg,
 	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
@@ -2154,17 +1877,36 @@  struct dram_timing_info dram_timing = {
 	.fsp_table = { 4000, 400, 100, },
 };
 
-/* dual die, single rank aka 1 GB (untested), 2 GB or 4 GB DDR timing config params */
-struct dram_timing_info dram_timing2 = {
-	.ddrc_cfg = ddr_ddrc_cfg2,
-	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg2),
-	.ddrphy_cfg = ddr_ddrphy_cfg,
-	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
-	.fsp_msg = ddr_dram_fsp_msg2,
-	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg2),
-	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
-	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
-	.ddrphy_pie = ddr_phy_pie,
-	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
-	.fsp_table = { 4000, 400, 100, },
-};
+static void apply_cfg_patch(struct dram_cfg_param *cfg, int cfg_sz,
+			    struct dram_cfg_param *patch, int patch_sz)
+{
+	int i, j;
+
+	for (i = 0; i < cfg_sz; i++)
+		for (j = 0; j < patch_sz; j++)
+			if (cfg[i].reg == patch[j].reg)
+				cfg[i].val = patch[j].val;
+}
+
+void lpddr4_single_rank_training_patch(void)
+{
+	apply_cfg_patch(ddr_ddrc_cfg, ARRAY_SIZE(ddr_ddrc_cfg),
+			ddr_ddrc_cfg_single_rank_patch,
+			ARRAY_SIZE(ddr_ddrc_cfg_single_rank_patch));
+
+	apply_cfg_patch(ddr_fsp0_cfg, ARRAY_SIZE(ddr_fsp0_cfg),
+			ddr_fsp0_cfg_single_rank_patch,
+			ARRAY_SIZE(ddr_fsp0_cfg_single_rank_patch));
+
+	apply_cfg_patch(ddr_fsp1_cfg, ARRAY_SIZE(ddr_fsp1_cfg),
+			ddr_fsp1_cfg_single_rank_patch,
+			ARRAY_SIZE(ddr_fsp1_cfg_single_rank_patch));
+
+	apply_cfg_patch(ddr_fsp2_cfg, ARRAY_SIZE(ddr_fsp2_cfg),
+			ddr_fsp2_cfg_single_rank_patch,
+			ARRAY_SIZE(ddr_fsp2_cfg_single_rank_patch));
+
+	apply_cfg_patch(ddr_fsp0_2d_cfg, ARRAY_SIZE(ddr_fsp0_2d_cfg),
+			ddr_fsp0_2d_cfg_single_rank_patch,
+			ARRAY_SIZE(ddr_fsp0_2d_cfg_single_rank_patch));
+}
diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.h b/board/toradex/verdin-imx8mp/lpddr4_timing.h
new file mode 100644
index 00000000000..95e74e37baf
--- /dev/null
+++ b/board/toradex/verdin-imx8mp/lpddr4_timing.h
@@ -0,0 +1,11 @@ 
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2022 Toradex
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+void lpddr4_single_rank_training_patch(void);
+
+#endif /* __LPDDR4_TIMING_H__ */
diff --git a/board/toradex/verdin-imx8mp/spl.c b/board/toradex/verdin-imx8mp/spl.c
index 7b383cc0d53..ab5bcbc0929 100644
--- a/board/toradex/verdin-imx8mp/spl.c
+++ b/board/toradex/verdin-imx8mp/spl.c
@@ -21,8 +21,7 @@ 
 #include <dm/uclass.h>
 #include <power/pmic.h>
 #include <power/pca9450.h>
-
-extern struct dram_timing_info dram_timing2;
+#include "lpddr4_timing.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -38,7 +37,8 @@  void spl_dram_init(void)
 	 */
 	if (ddr_init(&dram_timing)) {
 		printf("Dual rank failed, attempting single rank configuration.\n");
-		ddr_init(&dram_timing2);
+		lpddr4_single_rank_training_patch();
+		ddr_init(&dram_timing);
 	}
 }