| Message ID | 20230403060411.223861-1-patrice.chotard@foss.st.com |
|---|---|
| State | Accepted |
| Commit | 60edabc0a38e9f5ee0d84dad19710873fabac5e7 |
| Delegated to: | Patrice Chotard |
| Headers | show |
| Series | ARM: dts: stm32: Add QSPI support on STM32MP13x SoC family | expand |
Hi, On 4/3/23 08:04, Patrice Chotard wrote: > Add QSPI support on STM32MP13x SoC family > > Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> > --- > > arch/arm/dts/stm32mp131.dtsi | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi > index 3cf51f09bcb..5a064d5566e 100644 > --- a/arch/arm/dts/stm32mp131.dtsi > +++ b/arch/arm/dts/stm32mp131.dtsi > @@ -191,6 +191,21 @@ > dma-requests = <48>; > }; > > + qspi: spi@58003000 { > + compatible = "st,stm32f469-qspi"; > + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; > + reg-names = "qspi", "qspi_mm"; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, > + <&mdma 26 0x2 0x10100008 0x0 0x0>; > + dma-names = "tx", "rx"; > + clocks = <&rcc QSPI_K>; > + resets = <&rcc QSPI_R>; > + status = "disabled"; > + }; > + > sdmmc1: mmc@58005000 { > compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; > arm,primecell-periphid = <0x20253180>; Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Thanks Patrick
On 4/3/23 09:45, Patrick DELAUNAY wrote: > Hi, > > On 4/3/23 08:04, Patrice Chotard wrote: >> Add QSPI support on STM32MP13x SoC family >> >> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> >> --- >> >> arch/arm/dts/stm32mp131.dtsi | 15 +++++++++++++++ >> 1 file changed, 15 insertions(+) >> >> diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi >> index 3cf51f09bcb..5a064d5566e 100644 >> --- a/arch/arm/dts/stm32mp131.dtsi >> +++ b/arch/arm/dts/stm32mp131.dtsi >> @@ -191,6 +191,21 @@ >> dma-requests = <48>; >> }; >> + qspi: spi@58003000 { >> + compatible = "st,stm32f469-qspi"; >> + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; >> + reg-names = "qspi", "qspi_mm"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; >> + dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, >> + <&mdma 26 0x2 0x10100008 0x0 0x0>; >> + dma-names = "tx", "rx"; >> + clocks = <&rcc QSPI_K>; >> + resets = <&rcc QSPI_R>; >> + status = "disabled"; >> + }; >> + >> sdmmc1: mmc@58005000 { >> compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; >> arm,primecell-periphid = <0x20253180>; > > > > Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> > > Thanks > Patrick > > > > Applied on u-boot-stm/master, thanks Patrice
diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index 3cf51f09bcb..5a064d5566e 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -191,6 +191,21 @@ dma-requests = <48>; }; + qspi: spi@58003000 { + compatible = "st,stm32f469-qspi"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, + <&mdma 26 0x2 0x10100008 0x0 0x0>; + dma-names = "tx", "rx"; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; + status = "disabled"; + }; + sdmmc1: mmc@58005000 { compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x20253180>;
Add QSPI support on STM32MP13x SoC family Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> --- arch/arm/dts/stm32mp131.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+)