[v3,11/16] x86: coreboot: Scan PCI after relocation

Message ID	20230327041551.1757316-6-sjg@chromium.org
State	Superseded
Delegated to:	Bin Meng
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Simon Glass <sjg@chromium.org> To: U-Boot Mailing List <u-boot@lists.denx.de> Cc: Bin Meng <bmeng.cn@gmail.com>, Simon Glass <sjg@chromium.org> Subject: [PATCH v3 11/16] x86: coreboot: Scan PCI after relocation Date: Mon, 27 Mar 2023 17:15:45 +1300 Message-Id: <20230327041551.1757316-6-sjg@chromium.org> In-Reply-To: <20230327041551.1757316-1-sjg@chromium.org> References: <20230327041551.1757316-1-sjg@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	x86: Various minor enhancements for coreboot \| expand [v3,00/16] x86: Various minor enhancements for coreboot [v3,01/16] mtrr: Don't show an invalid CPU number [v3,02/16] x86: Adjust search range for sysinfo table [v3,03/16] input: Flush the keyboard buffer before resetting it [v3,04/16] acpi: Create a new Kconfig for ACPI [v3,05/16] acpi: Move the table-finding functions into the libary [v3,06/16] x86: coreboot: Collect the address of the ACPI tables [v3,07/16] x86: Allow locating the UART from ACPI tables [v3,08/16] pci: coreboot: Don't read regions when booting [v3,09/16] x86: coreboot: Use a memory-mapped UART [v3,10/16] x86: coreboot: Document how to enable the debug UART [v3,11/16] x86: coreboot: Scan PCI after relocation [v3,12/16] x86: coreboot: Log function names and line numbers [v3,13/16] x86: coreboot: Show unimplemented sysinfo tags [v3,14/16] x86: nvme: coreboot: Enable NVMe [v3,15/16] coreboot: Enable ms command [v3,16/16] x86: Allow locating UARTs by device ID

Message ID

20230327041551.1757316-6-sjg@chromium.org

State

Superseded

Delegated to:

Bin Meng

Headers

From: Simon Glass <sjg@chromium.org>
To: U-Boot Mailing List <u-boot@lists.denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>,
	Simon Glass <sjg@chromium.org>
Subject: [PATCH v3 11/16] x86: coreboot: Scan PCI after relocation
Date: Mon, 27 Mar 2023 17:15:45 +1300
Message-Id: <20230327041551.1757316-6-sjg@chromium.org>
In-Reply-To: <20230327041551.1757316-1-sjg@chromium.org>
References: <20230327041551.1757316-1-sjg@chromium.org>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: list
Errors-To: u-boot-bounces@lists.denx.de
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>

Series

x86: Various minor enhancements for coreboot | expand

Commit Message

Simon Glass March 27, 2023, 4:15 a.m. UTC

Enable this so that PCI devices can be used correctly without needing
to do a manual scan.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

(no changes since v1)

 configs/coreboot_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig
index fb4d1751108f..1bbb358a0220 100644
--- a/configs/coreboot_defconfig
+++ b/configs/coreboot_defconfig
@@ -18,6 +18,7 @@  CONFIG_PRE_CONSOLE_BUFFER=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_LAST_STAGE_INIT=y
+CONFIG_PCI_INIT_R=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PBSIZE=532
 CONFIG_CMD_IDE=y

[v3,11/16] x86: coreboot: Scan PCI after relocation

Commit Message

Patch