diff mbox series

[v1,1/1] arch: arm: zynqmp: mp.c: tcminit halt both cores in split mode

Message ID 20230323082506.31576-1-neal.frager@amd.com
State Accepted
Commit d58acf644f6e79ff36b990cb2ed4d88541c990df
Delegated to: Michal Simek
Headers show
Series [v1,1/1] arch: arm: zynqmp: mp.c: tcminit halt both cores in split mode | expand

Commit Message

Neal Frager March 23, 2023, 8:25 a.m. UTC
The "zynqmp tcminit split" command should halt both cores and not just RPU1
when configuring the TCM memory for split mode.

Signed-off-by: Neal Frager <neal.frager@amd.com>
---
 arch/arm/mach-zynqmp/mp.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Michal Simek March 28, 2023, 6:37 a.m. UTC | #1
On 3/23/23 09:25, Neal Frager wrote:
> The "zynqmp tcminit split" command should halt both cores and not just RPU1
> when configuring the TCM memory for split mode.
> 
> Signed-off-by: Neal Frager <neal.frager@amd.com>
> ---
>   arch/arm/mach-zynqmp/mp.c | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c
> index 4f1ed44afb..2407eaf00b 100644
> --- a/arch/arm/mach-zynqmp/mp.c
> +++ b/arch/arm/mach-zynqmp/mp.c
> @@ -244,8 +244,10 @@ void initialize_tcm(bool mode)
>   		release_r5_reset(ZYNQMP_CORE_RPU0, LOCK);
>   	} else {
>   		set_r5_tcm_mode(SPLIT);
> +		set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, SPLIT);
>   		set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT);
>   		enable_clock_r5();
> +		release_r5_reset(ZYNQMP_CORE_RPU0, SPLIT);
>   		release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT);
>   	}
>   }

Applied.
M
diff mbox series

Patch

diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c
index 4f1ed44afb..2407eaf00b 100644
--- a/arch/arm/mach-zynqmp/mp.c
+++ b/arch/arm/mach-zynqmp/mp.c
@@ -244,8 +244,10 @@  void initialize_tcm(bool mode)
 		release_r5_reset(ZYNQMP_CORE_RPU0, LOCK);
 	} else {
 		set_r5_tcm_mode(SPLIT);
+		set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, SPLIT);
 		set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT);
 		enable_clock_r5();
+		release_r5_reset(ZYNQMP_CORE_RPU0, SPLIT);
 		release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT);
 	}
 }