diff mbox series

[RESEND,v2] arm: mvebu: Power up 2nd SATA port for Thecus N2350

Message ID 20230207010012.1759-1-mibodhi@gmail.com
State Accepted
Commit 384e2d396c378063749849739e6b528be59c4071
Delegated to: Stefan Roese
Headers show
Series [RESEND,v2] arm: mvebu: Power up 2nd SATA port for Thecus N2350 | expand

Commit Message

Tony Dinh Feb. 7, 2023, 1 a.m. UTC
Currently, only the 1st SATA port is powered up (by GPIO1 12).
Add GPIO1 13 in board initialization to power up the 2nd SATA port.

Note that this patch depends on the initial add-support patch:
https://patchwork.ozlabs.org/project/uboot/patch/20230201231306.7010-1-mibodhi@gmail.com/

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
---

Changes in v2:
- Use BIT macros to make it easier to see which GPIOs are used.
- Resent to correct missing BIT(0) in N2350_GPP_OUT_VAL_MID

 board/thecus/n2350/n2350.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Stefan Roese Feb. 7, 2023, 8:19 a.m. UTC | #1
On 2/7/23 02:00, Tony Dinh wrote:
> Currently, only the 1st SATA port is powered up (by GPIO1 12).
> Add GPIO1 13 in board initialization to power up the 2nd SATA port.
> 
> Note that this patch depends on the initial add-support patch:
> https://patchwork.ozlabs.org/project/uboot/patch/20230201231306.7010-1-mibodhi@gmail.com/
> 
> Signed-off-by: Tony Dinh <mibodhi@gmail.com>

Reviewed-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan

> ---
> 
> Changes in v2:
> - Use BIT macros to make it easier to see which GPIOs are used.
> - Resent to correct missing BIT(0) in N2350_GPP_OUT_VAL_MID
> 
>   board/thecus/n2350/n2350.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/board/thecus/n2350/n2350.c b/board/thecus/n2350/n2350.c
> index 4cfdfba662..fd8f95f944 100644
> --- a/board/thecus/n2350/n2350.c
> +++ b/board/thecus/n2350/n2350.c
> @@ -24,8 +24,8 @@ DECLARE_GLOBAL_DATA_PTR;
>   
>   #define N2350_GPP_OUT_ENA_LOW	(~(BIT(20) | BIT(21) | BIT(24)))
>   #define N2350_GPP_OUT_ENA_MID	(~(BIT(12) | BIT(13) | BIT(16) | BIT(19) | BIT(22)))
> -#define N2350_GPP_OUT_VAL_LOW	0x1200000
> -#define N2350_GPP_OUT_VAL_MID	0x1001
> +#define N2350_GPP_OUT_VAL_LOW	(BIT(21) | BIT(24))
> +#define N2350_GPP_OUT_VAL_MID	(BIT(0) | BIT(12) | BIT(13))
>   #define N2350_GPP_POL_LOW	0x0
>   #define N2350_GPP_POL_MID	0x0
>   

Viele Grüße,
Stefan Roese
Stefan Roese Feb. 13, 2023, 2 p.m. UTC | #2
On 2/7/23 02:00, Tony Dinh wrote:
> Currently, only the 1st SATA port is powered up (by GPIO1 12).
> Add GPIO1 13 in board initialization to power up the 2nd SATA port.
> 
> Note that this patch depends on the initial add-support patch:
> https://patchwork.ozlabs.org/project/uboot/patch/20230201231306.7010-1-mibodhi@gmail.com/
> 
> Signed-off-by: Tony Dinh <mibodhi@gmail.com>

Applied to u-boot-marvell/master

Thanks,
Stefan

> ---
> 
> Changes in v2:
> - Use BIT macros to make it easier to see which GPIOs are used.
> - Resent to correct missing BIT(0) in N2350_GPP_OUT_VAL_MID
> 
>   board/thecus/n2350/n2350.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/board/thecus/n2350/n2350.c b/board/thecus/n2350/n2350.c
> index 4cfdfba662..fd8f95f944 100644
> --- a/board/thecus/n2350/n2350.c
> +++ b/board/thecus/n2350/n2350.c
> @@ -24,8 +24,8 @@ DECLARE_GLOBAL_DATA_PTR;
>   
>   #define N2350_GPP_OUT_ENA_LOW	(~(BIT(20) | BIT(21) | BIT(24)))
>   #define N2350_GPP_OUT_ENA_MID	(~(BIT(12) | BIT(13) | BIT(16) | BIT(19) | BIT(22)))
> -#define N2350_GPP_OUT_VAL_LOW	0x1200000
> -#define N2350_GPP_OUT_VAL_MID	0x1001
> +#define N2350_GPP_OUT_VAL_LOW	(BIT(21) | BIT(24))
> +#define N2350_GPP_OUT_VAL_MID	(BIT(0) | BIT(12) | BIT(13))
>   #define N2350_GPP_POL_LOW	0x0
>   #define N2350_GPP_POL_MID	0x0
>   

Viele Grüße,
Stefan Roese
diff mbox series

Patch

diff --git a/board/thecus/n2350/n2350.c b/board/thecus/n2350/n2350.c
index 4cfdfba662..fd8f95f944 100644
--- a/board/thecus/n2350/n2350.c
+++ b/board/thecus/n2350/n2350.c
@@ -24,8 +24,8 @@  DECLARE_GLOBAL_DATA_PTR;
 
 #define N2350_GPP_OUT_ENA_LOW	(~(BIT(20) | BIT(21) | BIT(24)))
 #define N2350_GPP_OUT_ENA_MID	(~(BIT(12) | BIT(13) | BIT(16) | BIT(19) | BIT(22)))
-#define N2350_GPP_OUT_VAL_LOW	0x1200000
-#define N2350_GPP_OUT_VAL_MID	0x1001
+#define N2350_GPP_OUT_VAL_LOW	(BIT(21) | BIT(24))
+#define N2350_GPP_OUT_VAL_MID	(BIT(0) | BIT(12) | BIT(13))
 #define N2350_GPP_POL_LOW	0x0
 #define N2350_GPP_POL_MID	0x0