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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id o13-20020a92d38d000000b00302bb083c2bsm4103194ilo.21.2023.01.30.07.17.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 07:17:47 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Tom Rini , Simon Glass , Kever Yang , Philipp Tomsich Subject: [PATCH 134/171] Correct SPL uses of ROCKCHIP_OTP Date: Mon, 30 Jan 2023 08:15:35 -0700 Message-Id: <20230130151612.212732-135-sjg@chromium.org> X-Mailer: git-send-email 2.39.1.456.gfc5497dd1b-goog In-Reply-To: <20230130151612.212732-102-sjg@chromium.org> References: <20230130151612.212732-102-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean This converts 2 usages of this option to the non-SPL form, since there is no SPL_ROCKCHIP_OTP defined in Kconfig Signed-off-by: Simon Glass --- arch/arm/mach-rockchip/misc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c index 437c7cf896a..b350f18f114 100644 --- a/arch/arm/mach-rockchip/misc.c +++ b/arch/arm/mach-rockchip/misc.c @@ -60,7 +60,7 @@ int rockchip_cpuid_from_efuse(const u32 cpuid_offset, const u32 cpuid_length, u8 *cpuid) { -#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) || CONFIG_IS_ENABLED(ROCKCHIP_OTP) +#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) || IS_ENABLED(CONFIG_ROCKCHIP_OTP) struct udevice *dev; int ret; @@ -68,7 +68,7 @@ int rockchip_cpuid_from_efuse(const u32 cpuid_offset, #if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(rockchip_efuse), &dev); -#elif CONFIG_IS_ENABLED(ROCKCHIP_OTP) +#elif IS_ENABLED(CONFIG_ROCKCHIP_OTP) ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(rockchip_otp), &dev); #endif