[v1,06/16] ARM: tegra: Fix Tegra PWM parent clock

Message ID	20230129184123.36001-7-clamor95@gmail.com
State	Superseded
Delegated to:	Tom Warren
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Svyatoslav Ryhel <clamor95@gmail.com> To: Tom Warren <twarren@nvidia.com>, Alban Bedel <alban.bedel@avionic-design.de>, Stephen Warren <swarren@nvidia.com>, Marcel Ziswiler <marcel.ziswiler@toradex.com>, Allen Martin <amartin@nvidia.com>, Jagan Teki <jagan@amarulasolutions.com>, Lukasz Majewski <lukma@denx.de>, Marek Vasut <marex@denx.de>, Svyatoslav Ryhel <clamor95@gmail.com>, Ramin Khonsari <raminterex@yahoo.com>, Thierry Reding <thierry.reding@gmail.com>, Maxim Schwalm <maxim.schwalm@gmail.com>, Dmitry Osipenko <digetx@gmail.com> Cc: u-boot@lists.denx.de Subject: [PATCH v1 06/16] ARM: tegra: Fix Tegra PWM parent clock Date: Sun, 29 Jan 2023 20:41:13 +0200 Message-Id: <20230129184123.36001-7-clamor95@gmail.com> In-Reply-To: <20230129184123.36001-1-clamor95@gmail.com> References: <20230129184123.36001-1-clamor95@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	General Tegra improvements \| expand [v1,00/16] General Tegra improvements [v1,01/16] tegra30: clock: add EXTPERIPH [v1,02/16] ARM: t20/t30: swap host1x and disp1 clock parents [v1,03/16] ARM: tegra: clock: add clk_id_to_pll_id helper [v1,04/16] ARM: tegra: clock: add clock_decode_pair helper [v1,05/16] ARM: tegra30: add PLLD to pll setup [v1,06/16] ARM: tegra: Fix Tegra PWM parent clock [v1,07/16] spi: tegra20_slink: accept any word length [v1,08/16] ARM: tegra: provide default USB gadget setup [v1,09/16] ARM: tegra: add late init support [v1,10/16] ARM: tegra: create common pre-dm i2c write [v1,11/16] board: tegra124: switch to updated pre-dm i2c write [v1,12/16] board: tegra30: switch to updated pre-dm i2c write [v1,13/16] ARM: tegra: expose crypto module for all Tegra SoCs [v1,14/16] ARM: tegra: crypto: extend crypto functional [v1,15/16] ARM: tegra30: implement BCT patching [v1,16/16] ARM: tegra20: implement BCT patching

Message ID

20230129184123.36001-7-clamor95@gmail.com

State

Superseded

Delegated to:

Tom Warren

Headers

From: Svyatoslav Ryhel <clamor95@gmail.com>
To: Tom Warren <twarren@nvidia.com>,
 Alban Bedel <alban.bedel@avionic-design.de>,
 Stephen Warren <swarren@nvidia.com>,
 Marcel Ziswiler <marcel.ziswiler@toradex.com>,
 Allen Martin <amartin@nvidia.com>, Jagan Teki <jagan@amarulasolutions.com>,
 Lukasz Majewski <lukma@denx.de>, Marek Vasut <marex@denx.de>,
 Svyatoslav Ryhel <clamor95@gmail.com>,
 Ramin Khonsari <raminterex@yahoo.com>,
 Thierry Reding <thierry.reding@gmail.com>,
 Maxim Schwalm <maxim.schwalm@gmail.com>, Dmitry Osipenko <digetx@gmail.com>
Cc: u-boot@lists.denx.de
Subject: [PATCH v1 06/16] ARM: tegra: Fix Tegra PWM parent clock
Date: Sun, 29 Jan 2023 20:41:13 +0200
Message-Id: <20230129184123.36001-7-clamor95@gmail.com>
In-Reply-To: <20230129184123.36001-1-clamor95@gmail.com>
References: <20230129184123.36001-1-clamor95@gmail.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: list
Errors-To: u-boot-bounces@lists.denx.de
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>

Series

General Tegra improvements | expand

Commit Message

Svyatoslav Ryhel Jan. 29, 2023, 6:41 p.m. UTC

Default parent clock for the PWM on Tegra is a 32kHz clock and
is unable to support the requested PWM period.

Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by
updating the parent clock for the PWM to be the PLL_P.

This commit is equivalent to Linux kernel commit:
https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 arch/arm/dts/tegra114.dtsi           |  2 +-
 arch/arm/dts/tegra124.dtsi           |  2 +-
 arch/arm/mach-tegra/tegra114/clock.c |  2 +-
 arch/arm/mach-tegra/tegra124/clock.c |  2 +-
 arch/arm/mach-tegra/tegra20/clock.c  |  2 +-
 arch/arm/mach-tegra/tegra210/clock.c |  2 +-
 arch/arm/mach-tegra/tegra30/clock.c  |  2 +-
 drivers/pwm/tegra_pwm.c              | 10 ++++++----
 8 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index 8932ea3afd..68ee7f3165 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -312,7 +312,7 @@ 
 	};
 
 	pwm: pwm@7000a000 {
-		compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
+		compatible = "nvidia,tegra114-pwm";
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
 		clocks = <&tegra_car TEGRA114_CLK_PWM>;
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi
index f473ba28e4..ffec9cae09 100644
--- a/arch/arm/dts/tegra124.dtsi
+++ b/arch/arm/dts/tegra124.dtsi
@@ -377,7 +377,7 @@ 
 	};
 
 	pwm: pwm@7000a000 {
-		compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
+		compatible = "nvidia,tegra124-pwm", "nvidia,tegra114-pwm";
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
 		clocks = <&tegra_car TEGRA124_CLK_PWM>;
diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c
index fb9780f826..1eab91494f 100644
--- a/arch/arm/mach-tegra/tegra114/clock.c
+++ b/arch/arm/mach-tegra/tegra114/clock.c
@@ -785,7 +785,7 @@  struct periph_clk_init periph_clk_init_table[] = {
 	{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
-	{ PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
+	{ PERIPH_ID_PWM, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index ffa5437630..fe3406126a 100644
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -1211,7 +1211,7 @@  struct periph_clk_init periph_clk_init_table[] = {
 	{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
-	{ PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
+	{ PERIPH_ID_PWM, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c
index 279b21f841..aa75284bb5 100644
--- a/arch/arm/mach-tegra/tegra20/clock.c
+++ b/arch/arm/mach-tegra/tegra20/clock.c
@@ -802,7 +802,7 @@  struct periph_clk_init periph_clk_init_table[] = {
 	{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
-	{ PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
+	{ PERIPH_ID_PWM, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c
index 1c991bbeab..79a1933322 100644
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -1292,7 +1292,7 @@  struct periph_clk_init periph_clk_init_table[] = {
 	{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
-	{ PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
+	{ PERIPH_ID_PWM, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c
index 3b0b84f8fd..f9a4fdb71e 100644
--- a/arch/arm/mach-tegra/tegra30/clock.c
+++ b/arch/arm/mach-tegra/tegra30/clock.c
@@ -849,7 +849,7 @@  struct periph_clk_init periph_clk_init_table[] = {
 	{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
-	{ PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
+	{ PERIPH_ID_PWM, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c
index 36c35c608b..95fc26458b 100644
--- a/drivers/pwm/tegra_pwm.c
+++ b/drivers/pwm/tegra_pwm.c
@@ -20,19 +20,21 @@  static int tegra_pwm_set_config(struct udevice *dev, uint channel,
 {
 	struct tegra_pwm_priv *priv = dev_get_priv(dev);
 	struct pwm_ctlr *regs = priv->regs;
+	const u32 pwm_max_freq = dev_get_driver_data(dev);
 	uint pulse_width;
 	u32 reg;
 
 	if (channel >= 4)
 		return -EINVAL;
 	debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel);
-	/* We ignore the period here and just use 32KHz */
-	clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, 32768);
+
+	clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_PERIPH, pwm_max_freq);
 
 	pulse_width = duty_ns * 255 / period_ns;
 
 	reg = pulse_width << PWM_WIDTH_SHIFT;
 	reg |= 1 << PWM_DIVIDER_SHIFT;
+	reg |= PWM_ENABLE_MASK;
 	writel(reg, &regs[channel].control);
 	debug("%s: pulse_width=%u\n", __func__, pulse_width);
 
@@ -68,8 +70,8 @@  static const struct pwm_ops tegra_pwm_ops = {
 };
 
 static const struct udevice_id tegra_pwm_ids[] = {
-	{ .compatible = "nvidia,tegra124-pwm" },
-	{ .compatible = "nvidia,tegra20-pwm" },
+	{ .compatible = "nvidia,tegra20-pwm", .data = 48 * 1000000 },
+	{ .compatible = "nvidia,tegra114-pwm", .data = 408 * 1000000 },
 	{ }
 };

[v1,06/16] ARM: tegra: Fix Tegra PWM parent clock

Commit Message

Patch