diff --git a/Kconfig b/Kconfig
index a75cce7e28f..530577fbe97 100644
--- a/Kconfig
+++ b/Kconfig
@@ -461,7 +461,7 @@ config BUILD_TARGET
 	default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
 				ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
 	default "u-boot.kwb" if (ARCH_KIRKWOOD || ARMADA_32BIT) && !SPL
-	default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL
+	default "u-boot-with-spl.bin" if MPC85XX && !E500MC && !E5500 && !E6500 && SPL
 	default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
 	default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
 	help
diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index 6e1c44b7ea8..90347c964f1 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -24,7 +24,7 @@ config CHAIN_OF_TRUST
 	select SHA_HW_ACCEL
 	select SHA_PROG_HW_ACCEL
 	select ENV_IS_NOWHERE
-	select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
+	select SYS_CPC_REINIT_F if MPC85XX && !SYS_RAMBOOT
 	select CMD_EXT4 if ARM
 	select CMD_EXT4_WRITE if ARM
 	imply CMD_BLOB
@@ -246,9 +246,9 @@ endif
 
 config SYS_FSL_NUM_CC_PLLS
 	int "Number of clock control PLLs"
-	depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
+	depends on MPC85XX || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
 	default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2
-	default 6 if FSL_LSCH3 || MPC85xx
+	default 6 if FSL_LSCH3 || MPC85XX
 
 config SYS_FSL_ESDHC_BE
 	bool
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index eb39a03e997..71d5ea50f54 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -15,8 +15,8 @@ config MPC83XX
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 
-config MPC85xx
-	bool "MPC85xx"
+config MPC85XX
+	bool "MPC85XX"
 	select CREATE_ARCH_SYMLINK
 	select SYS_FSL_DDR
 	select SYS_FSL_DDR_BE
@@ -36,7 +36,7 @@ endchoice
 
 config FSL_LBC
 	def_bool y
-	depends on (MPC85xx || MPC83XX) && !FSL_IFC
+	depends on (MPC85XX || MPC83XX) && !FSL_IFC
 
 config HIGH_BATS
 	bool "Enable high BAT registers"
@@ -46,7 +46,7 @@ config HIGH_BATS
 
 config SYS_INIT_RAM_LOCK
 	bool "Lock some portion of L1 for initial ram stack"
-	depends on MPC83XX || MPC85xx
+	depends on MPC83XX || MPC85XX
 
 config SYS_SRIO
 	bool "Serial RapidIO support"
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index 5050f387a6e..e7baacf4b01 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 head-y := arch/powerpc/cpu/$(CPU)/start.o
-head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o
+head-$(CONFIG_MPC85XX) += arch/powerpc/cpu/mpc85xx/resetvec.o
 
 libs-y += arch/powerpc/cpu/$(CPU)/
 libs-y += arch/powerpc/cpu/
diff --git a/arch/powerpc/cpu/Makefile b/arch/powerpc/cpu/Makefile
index c56f0d78b2d..914f95ca674 100644
--- a/arch/powerpc/cpu/Makefile
+++ b/arch/powerpc/cpu/Makefile
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 obj-$(CONFIG_MPC83XX) += mpc8xxx/
-obj-$(CONFIG_MPC85xx) += mpc8xxx/
+obj-$(CONFIG_MPC85XX) += mpc8xxx/
 obj-$(CONFIG_MPC86xx) += mpc8xxx/
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index 5e58023bfa8..27e3437fd8e 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -6,7 +6,7 @@
 /*
  * CPU specific code for the MPC83XX family.
  *
- * Derived from the MPC8260 and MPC85xx.
+ * Derived from the MPC8260 and MPC85XX.
  */
 
 #include <common.h>
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index e813bf094d1..a31d5f94fd8 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1,5 +1,5 @@
 menu "mpc85xx CPU"
-	depends on MPC85xx
+	depends on MPC85XX
 
 config PPC_SPINTABLE_COMPATIBLE
 	depends on MP
@@ -19,7 +19,7 @@ config SYS_CPU
 
 config CMD_ERRATA
 	bool "Enable the 'errata' command"
-	depends on MPC85xx
+	depends on MPC85XX
 	default y
 	help
 	  This enables the 'errata' command which displays a list of errata
@@ -27,7 +27,7 @@ config CMD_ERRATA
 
 config FSL_PREPBL_ESDHC_BOOT_SECTOR
 	bool "Generate QorIQ pre-PBL eSDHC boot sector"
-	depends on MPC85xx
+	depends on MPC85XX
 	depends on SDCARD
 	help
 	  With this option final image would have prepended QorIQ pre-PBL eSDHC
@@ -943,7 +943,7 @@ config ARCH_T4240
 
 config MPC85XX_HAVE_RESET_VECTOR
 	bool "Indicate reset vector at CFG_RESET_VECTOR_ADDRESS - 0xffc"
-	depends on MPC85xx
+	depends on MPC85XX
 
 config BTB
 	bool "toggle branch predition"
@@ -986,7 +986,7 @@ config HETROGENOUS_CLUSTERS
 	bool
 
 config MAX_CPUS
-	int "Maximum number of CPUs permitted for MPC85xx"
+	int "Maximum number of CPUs permitted for MPC85XX"
 	default 12 if ARCH_T4240
 	default 8 if ARCH_P4080
 	default 4 if ARCH_B4860 || \
@@ -1506,14 +1506,14 @@ config SYS_FSL_USB_DUAL_PHY_ENABLE
 
 config SYS_MPC85XX_NO_RESETVEC
 	bool "Discard resetvec section and move bootpg section up"
-	depends on MPC85xx && !MPC85XX_HAVE_RESET_VECTOR
+	depends on MPC85XX && !MPC85XX_HAVE_RESET_VECTOR
 	help
 	  If this variable is specified, the section .resetvec is not kept and
 	  the section .bootpg is placed in the previous 4k of the .text section.
 
 config SPL_SYS_MPC85XX_NO_RESETVEC
 	bool "Discard resetvec section and move bootpg section up, in SPL"
-	depends on MPC85xx && SPL && !MPC85XX_HAVE_RESET_VECTOR
+	depends on MPC85XX && SPL && !MPC85XX_HAVE_RESET_VECTOR
 	help
 	  If this variable is specified, the section .resetvec is not kept and
 	  the section .bootpg is placed in the previous 4k of the .text section,
@@ -1521,7 +1521,7 @@ config SPL_SYS_MPC85XX_NO_RESETVEC
 
 config TPL_SYS_MPC85XX_NO_RESETVEC
 	bool "Discard resetvec section and move bootpg section up, in TPL"
-	depends on MPC85xx && TPL && !MPC85XX_HAVE_RESET_VECTOR
+	depends on MPC85XX && TPL && !MPC85XX_HAVE_RESET_VECTOR
 	help
 	  If this variable is specified, the section .resetvec is not kept and
 	  the section .bootpg is placed in the previous 4k of the .text section,
diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
index 79213348274..de6afaa2a6a 100644
--- a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
@@ -76,10 +76,10 @@ int is_serdes_configured(enum srds_prtcl prtcl)
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 pordevsr = in_be32(&gur->pordevsr);
-	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
-				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+	u32 srds_cfg = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >>
+				MPC85XX_PORDEVSR_IO_SEL_SHIFT;
 	int lane;
 
 	if (serdes1_prtcl_map & (1 << NONE))
diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
index e53dd43f31f..f7b462f6e6f 100644
--- a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
@@ -40,10 +40,10 @@ int is_serdes_configured(enum srds_prtcl device)
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
 	u32 pordevsr = in_be32(&gur->pordevsr);
-	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
-				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+	u32 srds_cfg = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >>
+				MPC85XX_PORDEVSR_IO_SEL_SHIFT;
 	const struct serdes_config *ptr;
 	int lane;
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index e8a3e82765f..9f9742f3aad 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -59,7 +59,7 @@ int checkcpu (void)
 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \
 	defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
 	ccsr_gur_t __iomem *gur =
-		(void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+		(void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 #endif
 
 	/*
@@ -76,8 +76,8 @@ int checkcpu (void)
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #else	/* CONFIG_FSL_CORENET */
 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
-	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
-		>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+	u32 ddr_ratio = ((gur->porpllsr) & MPC85XX_PORPLLSR_DDR_RATIO)
+		>> MPC85XX_PORPLLSR_DDR_RATIO_SHIFT;
 #else
 	u32 ddr_ratio = 0;
 #endif /* CONFIG_DYNAMIC_DDR_CLK_FREQ || CONFIG_STATIC_DDR_CLK_FREQ */
@@ -319,7 +319,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 	val |= 0x70000000;
 	mtspr(DBCR0,val);
 #else
-	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	/* Call board-specific preparation for reset */
 	board_reset_prepare();
@@ -436,7 +436,7 @@ int dram_init(void)
 
 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
 	{
-		ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+		ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 		unsigned int x = 10;
 		unsigned int i;
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 96183ac2c84..5e3e5a7b526 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -313,7 +313,7 @@ static void corenet_tb_init(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
 void fsl_erratum_a007212_workaround(void)
 {
-	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 ddr_pll_ratio;
 	u32 __iomem *plldgdcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c20);
 	u32 __iomem *plldadcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c28);
@@ -379,13 +379,13 @@ ulong cpu_init_f(void)
 {
 	extern void m8560_cpm_reset (void);
 #ifdef CFG_SYS_DCSRBAR_PHYS
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 #endif
 #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
 	struct law_entry law;
 #endif
 #ifdef CONFIG_ARCH_MPC8548
-	ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
+	ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85XX_ECM_ADDR);
 	uint svr = get_svr();
 
 	/*
@@ -455,7 +455,7 @@ int enable_cluster_l2(void)
 {
 	int i = 0;
 	u32 cluster, svr = get_svr();
-	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	struct ccsr_cluster_l2 __iomem *l2cache;
 
 	/* only the L2 of first cluster should be enabled as expected on T4080,
@@ -516,7 +516,7 @@ int l2cache_init(void)
 {
 	__maybe_unused u32 svr = get_svr();
 #ifdef CONFIG_L2_CACHE
-	ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR;
+	ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85XX_L2_ADDR;
 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 	struct ccsr_cluster_l2 * l2cache = (void __iomem *)CFG_SYS_FSL_CLUSTER_1_L2;
 #endif
@@ -534,20 +534,20 @@ int l2cache_init(void)
 	cache_ctl = l2cache->l2ctl;
 
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L2_ADDR)
-	if (cache_ctl & MPC85xx_L2CTL_L2E) {
+	if (cache_ctl & MPC85XX_L2CTL_L2E) {
 		/* Clear L2 SRAM memory-mapped base address */
 		out_be32(&l2cache->l2srbar0, 0x0);
 		out_be32(&l2cache->l2srbar1, 0x0);
 
 		/* set MBECCDIS=0, SBECCDIS=0 */
 		clrbits_be32(&l2cache->l2errdis,
-				(MPC85xx_L2ERRDIS_MBECC |
-				 MPC85xx_L2ERRDIS_SBECC));
+				(MPC85XX_L2ERRDIS_MBECC |
+				 MPC85XX_L2ERRDIS_SBECC));
 
 		/* set L2E=0, L2SRAM=0 */
 		clrbits_be32(&l2cache->l2ctl,
-				(MPC85xx_L2CTL_L2E |
-				 MPC85xx_L2CTL_L2SRAM_ENTIRE));
+				(MPC85XX_L2CTL_L2E |
+				 MPC85XX_L2CTL_L2SRAM_ENTIRE));
 	}
 #endif
 
@@ -588,11 +588,11 @@ int l2cache_init(void)
 		break;
 	}
 
-	if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
+	if (l2cache->l2ctl & MPC85XX_L2CTL_L2E) {
 		puts("already enabled");
 #if defined(CFG_SYS_INIT_L2_ADDR) && defined(CFG_SYS_FLASH_BASE)
 		u32 l2srbar = l2cache->l2srbar0;
-		if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
+		if (l2cache->l2ctl & MPC85XX_L2CTL_L2SRAM_ENTIRE
 				&& l2srbar >= CFG_SYS_FLASH_BASE) {
 			l2srbar = CFG_SYS_INIT_L2_ADDR;
 			l2cache->l2srbar0 = l2srbar;
@@ -821,7 +821,7 @@ int cpu_init_r(void)
 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
 	{
 		struct ccsr_usb_phy __iomem *usb_phy1 =
-			(void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR;
+			(void *)CFG_SYS_MPC85XX_USB1_PHY_ADDR;
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 		if (has_erratum_a006261())
 			fsl_erratum_a006261_workaround(usb_phy1);
@@ -833,7 +833,7 @@ int cpu_init_r(void)
 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
 	{
 		struct ccsr_usb_phy __iomem *usb_phy2 =
-			(void *)CFG_SYS_MPC85xx_USB2_PHY_ADDR;
+			(void *)CFG_SYS_MPC85XX_USB2_PHY_ADDR;
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 		if (has_erratum_a006261())
 			fsl_erratum_a006261_workaround(usb_phy2);
@@ -859,7 +859,7 @@ int cpu_init_r(void)
 
 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
 		struct ccsr_usb_phy __iomem *usb_phy =
-			(void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR;
+			(void *)CFG_SYS_MPC85XX_USB1_PHY_ADDR;
 		setbits_be32(&usb_phy->pllprg[1],
 			     CFG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
 			     CFG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
@@ -928,11 +928,11 @@ int cpu_init_r(void)
 		fsl_sata_reg_t *reg;
 
 		/* first SATA controller */
-		reg = (void *)CFG_SYS_MPC85xx_SATA1_ADDR;
+		reg = (void *)CFG_SYS_MPC85XX_SATA1_ADDR;
 		clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
 
 		/* second SATA controller */
-		reg = (void *)CFG_SYS_MPC85xx_SATA2_ADDR;
+		reg = (void *)CFG_SYS_MPC85XX_SATA2_ADDR;
 		clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
 	}
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index a67f37e3af9..de9dc2e77ea 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -85,10 +85,10 @@ void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 #endif
 #ifdef CONFIG_A003399_NOR_WORKAROUND
-	ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
+	ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85XX_L2_ADDR;
 	u32  *dst, *src;
 	void (*setup_ifc_sram)(void);
 	int i;
@@ -121,7 +121,7 @@ void cpu_init_early_f(void *fdt)
  * Hence specifically selecting CS3.
  */
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
-	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
+	setbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_LCLK_IFC_CS3);
 #endif
 
 #ifdef CONFIG_FSL_LAW
@@ -147,10 +147,10 @@ void cpu_init_early_f(void *fdt)
 	out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);
 
 	out_be32(&l2cache->l2errdis,
-		(MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
+		(MPC85XX_L2ERRDIS_MBECC | MPC85XX_L2ERRDIS_SBECC));
 
 	out_be32(&l2cache->l2ctl,
-		(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
+		(MPC85XX_L2CTL_L2E | MPC85XX_L2CTL_L2SRAM_ENTIRE));
 
 	/*
 	 * Copy the code in setup_ifc to L2SRAM. Do a word copy
@@ -170,8 +170,8 @@ void cpu_init_early_f(void *fdt)
 
 	/* CLEANUP */
 	clrbits_be32(&l2cache->l2ctl,
-			(MPC85xx_L2CTL_L2E |
-			 MPC85xx_L2CTL_L2SRAM_ENTIRE));
+			(MPC85XX_L2CTL_L2E |
+			 MPC85XX_L2CTL_L2SRAM_ENTIRE));
 	out_be32(&l2cache->l2srbar0, 0x0);
 #endif
 
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index e26436bf570..6bc5afe1126 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -220,7 +220,7 @@ static inline void ft_fixup_l2cache_compatible(void *blob, int off)
 /* return size in kilobytes */
 static inline u32 l2cache_size(void)
 {
-	volatile ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
+	volatile ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85XX_L2_ADDR;
 	volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
 	u32 ver = SVR_SOC_VER(get_svr());
 
@@ -507,7 +507,7 @@ static void ft_fixup_qe_snum(void *blob)
 #if defined(CONFIG_ARCH_P4080)
 static void fdt_fixup_usb(void *fdt)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
 	int off;
 
@@ -530,7 +530,7 @@ void fdt_fixup_dma3(void *blob)
 {
 	/* the 3rd DMA is not functional if SRIO2 is chosen */
 	int nodeoff;
-	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 #define CFG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
 #if defined(CONFIG_ARCH_T2080)
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 9b6577e547e..0862a1c51fe 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -122,7 +122,7 @@ int is_serdes_configured(enum srds_prtcl device)
 
 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 {
-	const ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	const ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 cfg = in_be32(&gur->rcwsr[4]);
 	int i;
 
@@ -193,7 +193,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 		u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
 {
-	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 cfg;
 	int lane;
 
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 7c2de02c4c5..95f2515390f 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -108,7 +108,7 @@ int serdes_get_bank_by_lane(int lane)
 
 int serdes_lane_enabled(int lane)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
 
 	int bank = lanes[lane].bank;
@@ -133,7 +133,7 @@ int serdes_lane_enabled(int lane)
 
 int is_serdes_configured(enum srds_prtcl device)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	/* Is serdes enabled at all? */
 	if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
@@ -169,7 +169,7 @@ int serdes_get_first_lane(enum srds_prtcl device)
 	u32 prtcl;
 	const ccsr_gur_t *gur;
 
-	gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR;
+	gur = (typeof(gur))CFG_SYS_MPC85XX_GUTS_ADDR;
 
 	/* Is serdes enabled at all? */
 	if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
@@ -251,7 +251,7 @@ void serdes_reset_rx(enum srds_prtcl device)
 	if (unlikely(device == NONE))
 		return;
 
-	gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR;
+	gur = (typeof(gur))CFG_SYS_MPC85XX_GUTS_ADDR;
 
 	/* Is serdes enabled at all? */
 	if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
@@ -491,7 +491,7 @@ void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init")));
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	int cfg;
 	serdes_corenet_t *srds_regs;
 #ifdef CONFIG_ARCH_P5040
diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c
index bcbdfac0279..0fe83e80024 100644
--- a/arch/powerpc/cpu/mpc85xx/interrupts.c
+++ b/arch/powerpc/cpu/mpc85xx/interrupts.c
@@ -6,7 +6,7 @@
  * (C) Copyright 2002 (440 port)
  * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
  *
- * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
+ * (C) Copyright 2003 Motorola Inc. (MPC85XX port)
  * Xianghua Xiao (X.Xiao@motorola.com)
  */
 
@@ -36,10 +36,10 @@ void interrupt_init_cpu(unsigned *decrementer_count)
 	ulong post_word = post_word_load();
 #endif
 
-	out_be32(&pic->gcr, MPC85xx_PICGCR_RST);
-	while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST)
+	out_be32(&pic->gcr, MPC85XX_PICGCR_RST);
+	while (in_be32(&pic->gcr) & MPC85XX_PICGCR_RST)
 		;
-	out_be32(&pic->gcr, MPC85xx_PICGCR_M);
+	out_be32(&pic->gcr, MPC85XX_PICGCR_M);
 	in_be32(&pic->gcr);
 
 	*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 7c47e415f05..3f159cc9d69 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -87,7 +87,7 @@ int cpu_status(u32 nr)
 #ifdef CONFIG_FSL_CORENET
 int cpu_disable(u32 nr)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	setbits_be32(&gur->coredisrl, 1 << nr);
 
@@ -95,7 +95,7 @@ int cpu_disable(u32 nr)
 }
 
 int is_core_disabled(int nr) {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 coredisrl = in_be32(&gur->coredisrl);
 
 	return (coredisrl & (1 << nr));
@@ -103,14 +103,14 @@ int is_core_disabled(int nr) {
 #else
 int cpu_disable(u32 nr)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	switch (nr) {
 	case 0:
-		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
+		setbits_be32(&gur->devdisr, MPC85XX_DEVDISR_CPU0);
 		break;
 	case 1:
-		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
+		setbits_be32(&gur->devdisr, MPC85XX_DEVDISR_CPU1);
 		break;
 	default:
 		printf("Invalid cpu number for disable %d\n", nr);
@@ -121,14 +121,14 @@ int cpu_disable(u32 nr)
 }
 
 int is_core_disabled(int nr) {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 devdisr = in_be32(&gur->devdisr);
 
 	switch (nr) {
 	case 0:
-		return (devdisr & MPC85xx_DEVDISR_CPU0);
+		return (devdisr & MPC85XX_DEVDISR_CPU0);
 	case 1:
-		return (devdisr & MPC85xx_DEVDISR_CPU1);
+		return (devdisr & MPC85XX_DEVDISR_CPU1);
 	default:
 		printf("Invalid cpu number for disable %d\n", nr);
 	}
@@ -264,7 +264,7 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
 	u32 mask = cpu_mask();
 	struct law_entry e;
 
-	gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	ccm = (void *)(CFG_SYS_FSL_CORENET_CCM_ADDR);
 	rcpm = (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
 	pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
@@ -336,8 +336,8 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
 	u32 up, cpu_up_mask, whoami;
 	u32 *table = (u32 *)&__spin_table;
 	volatile u32 bpcr;
-	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
-	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85XX_ECM_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
 	u32 devdisr;
 	int timeout = 10;
@@ -348,9 +348,9 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
 	/* disable time base at the platform */
 	devdisr = in_be32(&gur->devdisr);
 	if (whoami)
-		devdisr |= MPC85xx_DEVDISR_TB0;
+		devdisr |= MPC85XX_DEVDISR_TB0;
 	else
-		devdisr |= MPC85xx_DEVDISR_TB1;
+		devdisr |= MPC85XX_DEVDISR_TB1;
 	out_be32(&gur->devdisr, devdisr);
 
 	/* release the hounds */
@@ -382,9 +382,9 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
 
 	/* enable time base at the platform */
 	if (whoami)
-		devdisr |= MPC85xx_DEVDISR_TB1;
+		devdisr |= MPC85XX_DEVDISR_TB1;
 	else
-		devdisr |= MPC85xx_DEVDISR_TB0;
+		devdisr |= MPC85XX_DEVDISR_TB0;
 	out_be32(&gur->devdisr, devdisr);
 
 	/* readback to sync write */
@@ -393,7 +393,7 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
 	mtspr(SPRN_TBWU, 0);
 	mtspr(SPRN_TBWL, 0);
 
-	devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
+	devdisr &= ~(MPC85XX_DEVDISR_TB0 | MPC85XX_DEVDISR_TB1);
 	out_be32(&gur->devdisr, devdisr);
 
 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
index cbcb57fe3a5..2c45872f075 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
@@ -89,8 +89,8 @@ int is_serdes_configured(enum srds_prtcl device)
 
 void fsl_serdes_init(void)
 {
-	void *guts = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-	void *sd = (void *)CFG_SYS_MPC85xx_SERDES2_ADDR;
+	void *guts = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
+	void *sd = (void *)CFG_SYS_MPC85XX_SERDES2_ADDR;
 	u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS);
 	u32 srds1_io_sel, srds2_io_sel;
 	u32 tmp;
@@ -100,8 +100,8 @@ void fsl_serdes_init(void)
 	    serdes2_prtcl_map & (1 << NONE))
 		return;
 
-	srds1_io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
-				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+	srds1_io_sel = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >>
+				MPC85XX_PORDEVSR_IO_SEL_SHIFT;
 
 	/* parse the SRDS2_IO_SEL of PORDEVSR */
 	srds2_io_sel = (pordevsr & GUTS_PORDEVSR_SERDES2_IO_SEL)
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
index a48f3c15128..21128ccdbeb 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
@@ -52,10 +52,10 @@ int is_serdes_configured(enum srds_prtcl device)
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
 	u32 pordevsr = in_be32(&gur->pordevsr);
-	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
-				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+	u32 srds_cfg = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >>
+				MPC85XX_PORDEVSR_IO_SEL_SHIFT;
 	int lane;
 
 	if (serdes1_prtcl_map & (1 << NONE) &&
@@ -86,10 +86,10 @@ void fsl_serdes_init(void)
 		serdes2_prtcl_map |= (1 << lane_prtcl);
 	}
 
-	if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)
+	if (pordevsr & MPC85XX_PORDEVSR_SGMII1_DIS)
 		serdes2_prtcl_map &= ~(1 << SGMII_TSEC1);
 
-	if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)
+	if (pordevsr & MPC85XX_PORDEVSR_SGMII3_DIS)
 		serdes2_prtcl_map &= ~(1 << SGMII_TSEC3);
 
 	/* Set the first bit to indicate serdes has been initialized */
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
index 479ee085d3a..950ca9f957e 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
@@ -32,10 +32,10 @@ int is_serdes_configured(enum srds_prtcl prtcl)
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 pordevsr = in_be32(&gur->pordevsr);
-	u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
-				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+	u32 srds1_cfg = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >>
+				MPC85XX_PORDEVSR_IO_SEL_SHIFT;
 	int lane;
 
 	if (serdes1_prtcl_map & (1 << NONE))
diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
index 56e5ef6468c..51a57a52523 100644
--- a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
@@ -51,10 +51,10 @@ int is_serdes_configured(enum srds_prtcl device)
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
 	u32 pordevsr = in_be32(&gur->pordevsr);
-	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
-				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+	u32 srds_cfg = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >>
+				MPC85XX_PORDEVSR_IO_SEL_SHIFT;
 	int lane;
 
 	if (serdes1_prtcl_map & (1 << NONE) &&
diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
index 47f13e3c1cd..6dce81afa05 100644
--- a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
@@ -50,12 +50,12 @@ int is_serdes_configured(enum srds_prtcl prtcl)
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-	serdes_85xx_t *serdes = (void *)CFG_SYS_MPC85xx_SERDES1_ADDR;
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
+	serdes_85xx_t *serdes = (void *)CFG_SYS_MPC85XX_SERDES1_ADDR;
 
 	u32 pordevsr = in_be32(&gur->pordevsr);
-	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
-				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+	u32 srds_cfg = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >>
+				MPC85XX_PORDEVSR_IO_SEL_SHIFT;
 	int lane;
 	u32 mask, val;
 
diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
index 7a8f653727e..191573f79d6 100644
--- a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
@@ -35,10 +35,10 @@ int is_serdes_configured(enum srds_prtcl device)
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
 	u32 pordevsr = in_be32(&gur->pordevsr);
-	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
-				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+	u32 srds_cfg = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >>
+				MPC85XX_PORDEVSR_IO_SEL_SHIFT;
 	int lane;
 
 	if (serdes1_prtcl_map & (1 << NONE))
diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
index 8c5d82ae8ad..dfaa4850e6d 100644
--- a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
@@ -40,10 +40,10 @@ int is_serdes_configured(enum srds_prtcl prtcl)
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 pordevsr = in_be32(&gur->pordevsr);
-	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
-				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+	u32 srds_cfg = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >>
+				MPC85XX_PORDEVSR_IO_SEL_SHIFT;
 	int lane;
 
 	if (serdes1_prtcl_map & (1 << NONE))
diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c
index 3cf41ca76d5..3fb80441d99 100644
--- a/arch/powerpc/cpu/mpc85xx/qe_io.c
+++ b/arch/powerpc/cpu/mpc85xx/qe_io.c
@@ -20,7 +20,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
 	u32			pin_2bit_assign;
 	u32			pin_1bit_mask;
 	u32			tmp_val;
-	volatile ccsr_gur_t	*gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t	*gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	volatile par_io_t	*par_io = (volatile par_io_t *)
 						&(gur->qe_par_io);
 
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 9af40310b46..eb1ff3dbc10 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void get_sys_info(sys_info_t *sys_info)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 #ifdef CONFIG_FSL_CORENET
 	volatile ccsr_clk_t *clk = (void *)(CFG_SYS_FSL_CORENET_CLK_ADDR);
 	unsigned int cpu;
@@ -537,8 +537,8 @@ void get_sys_info(sys_info_t *sys_info)
 
 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
 	{
-		u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
-			>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+		u32 ddr_ratio = ((gur->porpllsr) & MPC85XX_PORPLLSR_DDR_RATIO)
+			>> MPC85XX_PORPLLSR_DDR_RATIO_SHIFT;
 		if (ddr_ratio != 0x7)
 			sys_info->freq_ddrbus = ddr_ratio * get_board_ddr_clk();
 	}
@@ -548,8 +548,8 @@ void get_sys_info(sys_info_t *sys_info)
 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
 	sys_info->freq_qe =  sys_info->freq_systembus;
 #else
-	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
-			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
+	qe_ratio = ((gur->porpllsr) & MPC85XX_PORPLLSR_QE_RATIO)
+			>> MPC85XX_PORPLLSR_QE_RATIO_SHIFT;
 	sys_info->freq_qe = qe_ratio * get_board_sys_clk();
 #endif
 #endif
@@ -575,7 +575,7 @@ int get_clocks(void)
 {
 	sys_info_t sys_info;
 #ifdef CONFIG_ARCH_MPC8544
-	volatile ccsr_gur_t *gur = (void *) CFG_SYS_MPC85xx_GUTS_ADDR;
+	volatile ccsr_gur_t *gur = (void *) CFG_SYS_MPC85XX_GUTS_ADDR;
 #endif
 	get_sys_info (&sys_info);
 	gd->cpu_clk = sys_info.freq_processor[0];
@@ -604,7 +604,7 @@ int get_clocks(void)
 	 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
 	 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
 	 */
-	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
+	if (gur->pordevsr2 & MPC85XX_PORDEVSR2_SEC_CFG)
 		gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
 	else
 		gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
index ce2b9c21667..8bf0350bdb6 100644
--- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
@@ -15,17 +15,17 @@ DECLARE_GLOBAL_DATA_PTR;
 ulong cpu_init_f(void)
 {
 #ifdef CFG_SYS_INIT_L2_ADDR
-	ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
+	ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85XX_L2_ADDR;
 
 	out_be32(&l2cache->l2srbar0, CFG_SYS_INIT_L2_ADDR);
 
 	/* set MBECCDIS=1, SBECCDIS=1 */
 	out_be32(&l2cache->l2errdis,
-		(MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
+		(MPC85XX_L2ERRDIS_MBECC | MPC85XX_L2ERRDIS_SBECC));
 
 	/* set L2E=1 & L2SRAM=001 */
 	out_be32(&l2cache->l2ctl,
-		(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
+		(MPC85XX_L2CTL_L2E | MPC85XX_L2CTL_L2SRAM_ENTIRE));
 #endif
 
 	return 0;
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 562b6993b9d..21ad14aef35 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -80,17 +80,17 @@
 
 /* Definitions from C header file asm/immap_85xx.h */
 
-#define CFG_SYS_MPC85xx_L2_OFFSET		0x20000
+#define CFG_SYS_MPC85XX_L2_OFFSET		0x20000
 
-#define MPC85xx_L2CTL				0x000
-#define MPC85xx_L2CTL_L2E			0x80000000
-#define MPC85xx_L2CTL_L2SRAM_ENTIRE		0x00010000
+#define MPC85XX_L2CTL				0x000
+#define MPC85XX_L2CTL_L2E			0x80000000
+#define MPC85XX_L2CTL_L2SRAM_ENTIRE		0x00010000
 
-#define MPC85xx_L2SRBAR0			0x100
+#define MPC85XX_L2SRBAR0			0x100
 
-#define MPC85xx_L2ERRDIS			0xe44
-#define MPC85xx_L2ERRDIS_MBECC			0x00000008
-#define MPC85xx_L2ERRDIS_SBECC			0x00000004
+#define MPC85XX_L2ERRDIS			0xe44
+#define MPC85XX_L2ERRDIS_MBECC			0x00000008
+#define MPC85XX_L2ERRDIS_SBECC			0x00000004
 
 /* Definitions from C header file fsl_esdhc.h */
 
@@ -127,14 +127,14 @@ bootsect:
 	.org 0x80 /* Start of configuration */
 	.Lconf_pair_start:
 
-	.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
+	.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85XX_L2_OFFSET + MPC85XX_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
 	.long CFG_SYS_INIT_L2_ADDR
 
-	.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
-	.long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC
+	.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85XX_L2_OFFSET + MPC85XX_L2ERRDIS /* Address: L2 cache error disable */
+	.long MPC85XX_L2ERRDIS_MBECC | MPC85XX_L2ERRDIS_SBECC
 
-	.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */
-	.long MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE
+	.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85XX_L2_OFFSET + MPC85XX_L2CTL /* Address: L2 configuration 0 */
+	.long MPC85XX_L2CTL_L2E | MPC85XX_L2CTL_L2SRAM_ENTIRE
 
 	.long CONFIG_SYS_CCSRBAR_DEFAULT + ESDHCCTL /* Address: eSDHC DMA control */
 	.long ESDHCCTL_SNOOP
@@ -1325,7 +1325,7 @@ ProgramCheck:
 	EXC_XFER_TEMPLATE(0x700, ProgramCheck, ProgramCheckException,
 		MSR_KERNEL, COPY_EE)
 
-	/* No FPU on MPC85xx.  This exception is not supposed to happen.
+	/* No FPU on MPC85XX.  This exception is not supposed to happen.
 	*/
 	STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
 	STD_EXCEPTION(0x0900, SystemCall, UnknownException)
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile
index e3a536d4f8c..abcde571ac2 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -17,7 +17,7 @@ ifdef MINIMAL
 obj-$(CONFIG_FSL_LAW) += law.o
 
 else
-obj-$(CONFIG_MPC85xx) += cpu.o
+obj-$(CONFIG_MPC85XX) += cpu.o
 obj-$(CONFIG_MPC86xx) += cpu.o
 
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 73d28f2a4e2..d4a91622d34 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -24,7 +24,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct cpu_type cpu_type_list[] = {
-#if defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC85XX)
 	CPU_TYPE_ENTRY(8533, 8533, 1),
 	CPU_TYPE_ENTRY(8535, 8535, 1),
 	CPU_TYPE_ENTRY(8536, 8536, 1),
@@ -104,7 +104,7 @@ static struct cpu_type cpu_type_list[] = {
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 static inline u32 init_type(u32 cluster, int init_id)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 	u32 type = in_be32(&gur->tp_ityp[idx]);
 
@@ -116,7 +116,7 @@ static inline u32 init_type(u32 cluster, int init_id)
 
 u32 compute_ppc_cpumask(void)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	int i = 0, count = 0;
 	u32 cluster, type, mask = 0;
 
@@ -140,7 +140,7 @@ u32 compute_ppc_cpumask(void)
 #ifdef CONFIG_HETROGENOUS_CLUSTERS
 u32 compute_dsp_cpumask(void)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	int i = CONFIG_DSP_CLUSTER_START, count = 0;
 	u32 cluster, type, dsp_mask = 0;
 
@@ -163,7 +163,7 @@ u32 compute_dsp_cpumask(void)
 
 int fsl_qoriq_dsp_core_to_cluster(unsigned int core)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	int count = 0, i = CONFIG_DSP_CLUSTER_START;
 	u32 cluster;
 
@@ -186,7 +186,7 @@ int fsl_qoriq_dsp_core_to_cluster(unsigned int core)
 
 int fsl_qoriq_core_to_cluster(unsigned int core)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	int i = 0, count = 0;
 	u32 cluster;
 
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 30042902487..6055f986b8b 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -17,7 +17,7 @@
 #include <phy.h>
 #include <hwconfig.h>
 
-#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
+#if defined(CONFIG_MP) && (defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx))
 static int ft_del_cpuhandle(void *blob, int cpuhandle)
 {
 	int off, ret = -FDT_ERR_NOTFOUND;
@@ -69,7 +69,7 @@ void ft_fixup_num_cores(void *blob) {
 	debug ("deleted %d extra core entry entries from device tree\n",
 								del_cores);
 }
-#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
+#endif /* defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx) */
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
index 7519b214969..7fae2befc35 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
@@ -12,7 +12,7 @@
 #include "../mpc83xx/elbc/elbc.h"
 #endif
 
-#ifdef CONFIG_MPC85xx
+#ifdef CONFIG_MPC85XX
 /* Boards should provide their own version of this if they use lbc sdram */
 static void __lbc_sdram_init(void)
 {
@@ -44,7 +44,7 @@ void init_early_memctl_regs(void)
 	clrsetbits_be32(&(LBC_BASE_ADDR)->lbcr, LBCR_BMT|LBCR_BMTPS, 0xf);
 #endif
 
-#ifdef CONFIG_MPC85xx
+#ifdef CONFIG_MPC85XX
 	/* if cs1 is already set via debugger, leave cs0/cs1 alone */
 	if (get_lbc_br(1) & BR_V)
 		init_br1 = 0;
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index 35409dc8824..b0183edb064 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -301,7 +301,7 @@ void init_laws(void)
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 	/* check RCW to get which port is used for boot */
-	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
 	u32 bootloc = in_be32(&gur->rcwsr[6]);
 	/*
 	 * in SRIO or PCIE boot we need to set specail LAWs for
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index c0b4a1217d3..89ee4ea1ac2 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -33,12 +33,12 @@
 	#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
 #endif
 	#define _DEVDISR_RMU   FSL_CORENET_DEVDISR_RMU
-	#define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
-#elif defined(CONFIG_MPC85xx)
-	#define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
-	#define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
-	#define _DEVDISR_RMU   MPC85xx_DEVDISR_RMSG
-	#define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
+	#define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85XX_GUTS_ADDR
+#elif defined(CONFIG_MPC85XX)
+	#define _DEVDISR_SRIO1 MPC85XX_DEVDISR_SRIO
+	#define _DEVDISR_SRIO2 MPC85XX_DEVDISR_SRIO
+	#define _DEVDISR_RMU   MPC85XX_DEVDISR_RMSG
+	#define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85XX_GUTS_ADDR
 #elif defined(CONFIG_MPC86xx)
 	#define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
 	#define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index f0702cab143..3d411eb8661 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -6,7 +6,7 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-#ifdef CONFIG_MPC85xx
+#ifdef CONFIG_MPC85XX
 #include <asm/config_mpc85xx.h>
 #endif
 
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index d990ecff96f..ae95d089cdd 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -3,10 +3,10 @@
  * Copyright 2011-2012 Freescale Semiconductor, Inc.
  */
 
-#ifndef _ASM_MPC85xx_CONFIG_H_
-#define _ASM_MPC85xx_CONFIG_H_
+#ifndef _ASM_MPC85XX_CONFIG_H_
+#define _ASM_MPC85XX_CONFIG_H_
 
-/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
+/* SoC specific defines for Freescale MPC85XX (PQ3) and QorIQ processors */
 
 #include <fsl_ddrc_version.h>
 
@@ -174,4 +174,4 @@
 
 #endif
 
-#endif /* _ASM_MPC85xx_CONFIG_H_ */
+#endif /* _ASM_MPC85XX_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 8d681a1cba6..3808b2b4bf4 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -9,7 +9,7 @@
 #include <config.h>
 #include <common.h>
 
-#ifdef CONFIG_MPC85xx
+#ifdef CONFIG_MPC85XX
 void lbc_sdram_init(void);
 #endif
 
@@ -48,7 +48,7 @@ void lbc_sdram_init(void);
 #endif
 #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8360)
 #define BR_MS_SDRAM			0x00000060	/* SDRAM */
-#elif defined(CONFIG_MPC85xx)
+#elif defined(CONFIG_MPC85XX)
 #define BR_MS_SDRAM			0x00000000	/* SDRAM */
 #endif
 #define BR_MS_UPMA			0x00000080	/* UPMA */
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index 0af3d8902ac..93c1dc4ccfe 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -18,15 +18,15 @@ struct srio_liodn_id_table {
 #define SET_SRIO_LIODN_1(port, idA) \
 	{ .id = { idA }, .num_ids = 1, .portid = port, \
 	  .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
-		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
+		+ CFG_SYS_MPC85XX_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
 	}
 
 #define SET_SRIO_LIODN_2(port, idA, idB) \
 	{ .id = { idA, idB }, .num_ids = 2, .portid = port, \
 	  .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
-		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
+		+ CFG_SYS_MPC85XX_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
 	  .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
-		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
+		+ CFG_SYS_MPC85XX_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
 	}
 
 #define SET_SRIO_LIODN_BASE(port, id_a) \
@@ -90,42 +90,42 @@ extern void fdt_fixup_liodn(void *blob);
 
 #define SET_GUTS_LIODN(compat, liodn, name, compatoff) \
 	SET_LIODN_ENTRY_1(compat, liodn, \
-		offsetof(ccsr_gur_t, name) + CFG_SYS_MPC85xx_GUTS_OFFSET, \
+		offsetof(ccsr_gur_t, name) + CFG_SYS_MPC85XX_GUTS_OFFSET, \
 		compatoff)
 
 #define SET_USB_LIODN(usbNum, compat, liodn) \
 	SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\
-		CFG_SYS_MPC85xx_USB##usbNum##_OFFSET)
+		CFG_SYS_MPC85XX_USB##usbNum##_OFFSET)
 
 #define SET_SATA_LIODN(sataNum, liodn) \
 	SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\
-		CFG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
+		CFG_SYS_MPC85XX_SATA##sataNum##_OFFSET)
 
 #define SET_PCI_LIODN(compat, pciNum, liodn) \
 	SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
-		CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+		CFG_SYS_MPC85XX_PCIE##pciNum##_OFFSET)
 
 #define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
 	SET_LIODN_ENTRY_1(compat, liodn,\
-		offsetof(ccsr_pcix_t, liodn_base) + CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
-		CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+		offsetof(ccsr_pcix_t, liodn_base) + CFG_SYS_MPC85XX_PCIE##pciNum##_OFFSET,\
+		CFG_SYS_MPC85XX_PCIE##pciNum##_OFFSET)
 
 /* reg nodes for DMA start @ 0x300 */
 #define SET_DMA_LIODN(dmaNum, compat, liodn) \
 	SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\
-		CFG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
+		CFG_SYS_MPC85XX_DMA##dmaNum##_OFFSET + 0x300)
 
 #define SET_SDHC_LIODN(sdhcNum, liodn) \
 	SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
-		CFG_SYS_MPC85xx_ESDHC_OFFSET)
+		CFG_SYS_MPC85XX_ESDHC_OFFSET)
 
 #define SET_QE_LIODN(liodn) \
 	SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
-		CFG_SYS_MPC85xx_QE_OFFSET)
+		CFG_SYS_MPC85XX_QE_OFFSET)
 
 #define SET_TDM_LIODN(liodn) \
 	SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
-		CFG_SYS_MPC85xx_TDM_OFFSET)
+		CFG_SYS_MPC85XX_TDM_OFFSET)
 
 #define SET_QMAN_LIODN(liodn) \
 	SET_LIODN_ENTRY_1("fsl,qman", liodn, \
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index 809ab1d4187..c2f12d76521 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -241,7 +241,7 @@ int fsl_pcie_init_board(int busno);
 	FT_FSL_PCIE3_SETUP; \
 	FT_FSL_PCIE4_SETUP;
 #define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP
-#elif defined(CONFIG_MPC85xx)
+#elif defined(CONFIG_MPC85XX)
 #define FSL_PCI_COMPAT	"fsl,mpc8540-pci"
 #ifdef CONFIG_SYS_FSL_PCIE_COMPAT
 #define FSL_PCIE_COMPAT	CONFIG_SYS_FSL_PCIE_COMPAT
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 2636cbbda88..404980c1f47 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -53,11 +53,11 @@ struct arch_global_data {
 # endif /* CONFIG_ARCH_MPC8360 */
 #endif
 #endif
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx)
 	u32 lbc_clk;
 	void *cpu;
-#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
-#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || \
+#endif /* CONFIG_MPC85XX || CONFIG_MPC86xx */
+#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85XX) || \
 		defined(CONFIG_MPC86xx)
 	u32 i2c1_clk;
 	u32 i2c2_clk;
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 7293720fb3c..616aac5c666 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * MPC85xx Internal Memory Map
+ * MPC85XX Internal Memory Map
  *
  * Copyright 2007-2012 Freescale Semiconductor, Inc.
  *
@@ -316,10 +316,10 @@ typedef struct ccsr_l2cache {
 	u8	res15[420];
 } ccsr_l2cache_t;
 
-#define MPC85xx_L2CTL_L2E			0x80000000
-#define MPC85xx_L2CTL_L2SRAM_ENTIRE		0x00010000
-#define MPC85xx_L2ERRDIS_MBECC			0x00000008
-#define MPC85xx_L2ERRDIS_SBECC			0x00000004
+#define MPC85XX_L2CTL_L2E			0x80000000
+#define MPC85XX_L2CTL_L2SRAM_ENTIRE		0x00010000
+#define MPC85XX_L2ERRDIS_MBECC			0x00000008
+#define MPC85XX_L2ERRDIS_SBECC			0x00000004
 
 /* DMA Registers */
 typedef struct ccsr_dma {
@@ -638,8 +638,8 @@ typedef struct ccsr_pic {
 	u32	frr;		/* Feature Reporting */
 	u8	res10[28];
 	u32	gcr;		/* Global Configuration */
-#define MPC85xx_PICGCR_RST	0x80000000
-#define MPC85xx_PICGCR_M	0x20000000
+#define MPC85XX_PICGCR_RST	0x80000000
+#define MPC85XX_PICGCR_M	0x20000000
 	u8	res11[92];
 	u32	vir;		/* Vendor Identification */
 	u8	res12[12];
@@ -1787,29 +1787,29 @@ typedef struct ccsr_rcpm {
 typedef struct ccsr_gur {
 	u32	porpllsr;	/* POR PLL ratio status */
 #ifdef CONFIG_ARCH_MPC8536
-#define MPC85xx_PORPLLSR_DDR_RATIO	0x3e000000
-#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	25
+#define MPC85XX_PORPLLSR_DDR_RATIO	0x3e000000
+#define MPC85XX_PORPLLSR_DDR_RATIO_SHIFT	25
 #elif defined(CONFIG_ARCH_C29X)
-#define MPC85xx_PORPLLSR_DDR_RATIO	0x00003f00
-#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	(9 - ((gur->pordevsr2 \
-					& MPC85xx_PORDEVSR2_DDR_SPD_0) \
-					>> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
+#define MPC85XX_PORPLLSR_DDR_RATIO	0x00003f00
+#define MPC85XX_PORPLLSR_DDR_RATIO_SHIFT	(9 - ((gur->pordevsr2 \
+					& MPC85XX_PORDEVSR2_DDR_SPD_0) \
+					>> MPC85XX_PORDEVSR2_DDR_SPD_0_SHIFT))
 #else
 #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
-#define MPC85xx_PORPLLSR_DDR_RATIO	0x00003f00
+#define MPC85XX_PORPLLSR_DDR_RATIO	0x00003f00
 #else
-#define MPC85xx_PORPLLSR_DDR_RATIO	0x00003e00
+#define MPC85XX_PORPLLSR_DDR_RATIO	0x00003e00
 #endif
-#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	9
+#define MPC85XX_PORPLLSR_DDR_RATIO_SHIFT	9
 #endif
-#define MPC85xx_PORPLLSR_QE_RATIO	0x3e000000
-#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT		25
-#define MPC85xx_PORPLLSR_PLAT_RATIO	0x0000003e
-#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT	1
+#define MPC85XX_PORPLLSR_QE_RATIO	0x3e000000
+#define MPC85XX_PORPLLSR_QE_RATIO_SHIFT		25
+#define MPC85XX_PORPLLSR_PLAT_RATIO	0x0000003e
+#define MPC85XX_PORPLLSR_PLAT_RATIO_SHIFT	1
 	u32	porbmsr;	/* POR boot mode status */
-#define MPC85xx_PORBMSR_HA		0x00070000
-#define MPC85xx_PORBMSR_HA_SHIFT	16
-#define MPC85xx_PORBMSR_ROMLOC_SHIFT	24
+#define MPC85XX_PORBMSR_HA		0x00070000
+#define MPC85XX_PORBMSR_HA_SHIFT	16
+#define MPC85XX_PORBMSR_ROMLOC_SHIFT	24
 #define PORBMSR_ROMLOC_SPI	0x6
 #define PORBMSR_ROMLOC_SDHC	0x7
 #define PORBMSR_ROMLOC_NAND_2K	0x9
@@ -1817,58 +1817,58 @@ typedef struct ccsr_gur {
 	u32	porimpscr;	/* POR I/O impedance status & control */
 	u32	pordevsr;	/* POR I/O device status regsiter */
 #if defined(CONFIG_ARCH_P1023)
-#define MPC85xx_PORDEVSR_SGMII1_DIS	0x10000000
-#define MPC85xx_PORDEVSR_SGMII2_DIS	0x08000000
-#define MPC85xx_PORDEVSR_TSEC1_PRTC	0x02000000
+#define MPC85XX_PORDEVSR_SGMII1_DIS	0x10000000
+#define MPC85XX_PORDEVSR_SGMII2_DIS	0x08000000
+#define MPC85XX_PORDEVSR_TSEC1_PRTC	0x02000000
 #else
-#define MPC85xx_PORDEVSR_SGMII1_DIS	0x20000000
-#define MPC85xx_PORDEVSR_SGMII2_DIS	0x10000000
+#define MPC85XX_PORDEVSR_SGMII1_DIS	0x20000000
+#define MPC85XX_PORDEVSR_SGMII2_DIS	0x10000000
 #endif
-#define MPC85xx_PORDEVSR_SGMII3_DIS	0x08000000
-#define MPC85xx_PORDEVSR_SGMII4_DIS	0x04000000
-#define MPC85xx_PORDEVSR_SRDS2_IO_SEL	0x38000000
-#define MPC85xx_PORDEVSR_PCI1		0x00800000
+#define MPC85XX_PORDEVSR_SGMII3_DIS	0x08000000
+#define MPC85XX_PORDEVSR_SGMII4_DIS	0x04000000
+#define MPC85XX_PORDEVSR_SRDS2_IO_SEL	0x38000000
+#define MPC85XX_PORDEVSR_PCI1		0x00800000
 #if defined(CONFIG_ARCH_P1023)
-#define MPC85xx_PORDEVSR_IO_SEL		0x00600000
-#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
+#define MPC85XX_PORDEVSR_IO_SEL		0x00600000
+#define MPC85XX_PORDEVSR_IO_SEL_SHIFT	21
 #else
 #if defined(CONFIG_ARCH_P1010)
-#define MPC85xx_PORDEVSR_IO_SEL		0x00600000
-#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
+#define MPC85XX_PORDEVSR_IO_SEL		0x00600000
+#define MPC85XX_PORDEVSR_IO_SEL_SHIFT	21
 #elif defined(CONFIG_ARCH_BSC9132)
-#define MPC85xx_PORDEVSR_IO_SEL		0x00FE0000
-#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	17
+#define MPC85XX_PORDEVSR_IO_SEL		0x00FE0000
+#define MPC85XX_PORDEVSR_IO_SEL_SHIFT	17
 #elif defined(CONFIG_ARCH_C29X)
-#define MPC85xx_PORDEVSR_IO_SEL		0x00e00000
-#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
+#define MPC85XX_PORDEVSR_IO_SEL		0x00e00000
+#define MPC85XX_PORDEVSR_IO_SEL_SHIFT	21
 #else
-#define MPC85xx_PORDEVSR_IO_SEL		0x00780000
-#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	19
+#define MPC85XX_PORDEVSR_IO_SEL		0x00780000
+#define MPC85XX_PORDEVSR_IO_SEL_SHIFT	19
 #endif /* if defined(CONFIG_ARCH_P1010) */
 #endif
-#define MPC85xx_PORDEVSR_PCI2_ARB	0x00040000
-#define MPC85xx_PORDEVSR_PCI1_ARB	0x00020000
-#define MPC85xx_PORDEVSR_PCI1_PCI32	0x00010000
-#define MPC85xx_PORDEVSR_PCI1_SPD	0x00008000
-#define MPC85xx_PORDEVSR_PCI2_SPD	0x00004000
-#define MPC85xx_PORDEVSR_DRAM_RTYPE	0x00000060
-#define MPC85xx_PORDEVSR_RIO_CTLS	0x00000008
-#define MPC85xx_PORDEVSR_RIO_DEV_ID	0x00000007
+#define MPC85XX_PORDEVSR_PCI2_ARB	0x00040000
+#define MPC85XX_PORDEVSR_PCI1_ARB	0x00020000
+#define MPC85XX_PORDEVSR_PCI1_PCI32	0x00010000
+#define MPC85XX_PORDEVSR_PCI1_SPD	0x00008000
+#define MPC85XX_PORDEVSR_PCI2_SPD	0x00004000
+#define MPC85XX_PORDEVSR_DRAM_RTYPE	0x00000060
+#define MPC85XX_PORDEVSR_RIO_CTLS	0x00000008
+#define MPC85XX_PORDEVSR_RIO_DEV_ID	0x00000007
 	u32	pordbgmsr;	/* POR debug mode status */
 	u32	pordevsr2;	/* POR I/O device status 2 */
 #if defined(CONFIG_ARCH_C29X)
-#define MPC85xx_PORDEVSR2_DDR_SPD_0	0x00000008
-#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT	3
+#define MPC85XX_PORDEVSR2_DDR_SPD_0	0x00000008
+#define MPC85XX_PORDEVSR2_DDR_SPD_0_SHIFT	3
 #endif
-#define MPC85xx_PORDEVSR2_SBC_MASK	0x10000000
+#define MPC85XX_PORDEVSR2_SBC_MASK	0x10000000
 /* The 8544 RM says this is bit 26, but it's really bit 24 */
-#define MPC85xx_PORDEVSR2_SEC_CFG	0x00000080
+#define MPC85XX_PORDEVSR2_SEC_CFG	0x00000080
 	u8	res1[8];
 	u32	gpporcr;	/* General-purpose POR configuration */
 	u8	res2[12];
 #if defined(CONFIG_ARCH_MPC8536)
 	u32	gencfgr;	/* General Configuration Register */
-#define MPC85xx_GENCFGR_SDHC_WP_INV	0x20000000
+#define MPC85XX_GENCFGR_SDHC_WP_INV	0x20000000
 #else
 	u32	gpiocr;		/* GPIO control */
 #endif
@@ -1879,248 +1879,248 @@ typedef struct ccsr_gur {
 	u8	res5[12];
 	u32	pmuxcr;		/* Alt. function signal multiplex control */
 #if defined(CONFIG_ARCH_P1010)
-#define MPC85xx_PMUXCR_TSEC1_0_1588		0x40000000
-#define MPC85xx_PMUXCR_TSEC1_0_RES		0xC0000000
-#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG	0x10000000
-#define MPC85xx_PMUXCR_TSEC1_1_GPIO_12		0x20000000
-#define MPC85xx_PMUXCR_TSEC1_1_RES		0x30000000
-#define MPC85xx_PMUXCR_TSEC1_2_DMA		0x04000000
-#define MPC85xx_PMUXCR_TSEC1_2_GPIO		0x08000000
-#define MPC85xx_PMUXCR_TSEC1_2_RES		0x0C000000
-#define MPC85xx_PMUXCR_TSEC1_3_RES		0x01000000
-#define MPC85xx_PMUXCR_TSEC1_3_GPIO_15		0x02000000
-#define MPC85xx_PMUXCR_IFC_ADDR16_SDHC		0x00400000
-#define MPC85xx_PMUXCR_IFC_ADDR16_USB		0x00800000
-#define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2	0x00C00000
-#define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC	0x00100000
-#define MPC85xx_PMUXCR_IFC_ADDR17_18_USB	0x00200000
-#define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA	0x00300000
-#define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA	0x00040000
-#define MPC85xx_PMUXCR_IFC_ADDR19_USB		0x00080000
-#define MPC85xx_PMUXCR_IFC_ADDR19_DMA		0x000C0000
-#define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA	0x00010000
-#define MPC85xx_PMUXCR_IFC_ADDR20_21_USB	0x00020000
-#define MPC85xx_PMUXCR_IFC_ADDR20_21_RES	0x00030000
-#define MPC85xx_PMUXCR_IFC_ADDR22_SDHC		0x00004000
-#define MPC85xx_PMUXCR_IFC_ADDR22_USB		0x00008000
-#define MPC85xx_PMUXCR_IFC_ADDR22_RES		0x0000C000
-#define MPC85xx_PMUXCR_IFC_ADDR23_SDHC		0x00001000
-#define MPC85xx_PMUXCR_IFC_ADDR23_USB		0x00002000
-#define MPC85xx_PMUXCR_IFC_ADDR23_RES		0x00003000
-#define MPC85xx_PMUXCR_IFC_ADDR24_SDHC		0x00000400
-#define MPC85xx_PMUXCR_IFC_ADDR24_USB		0x00000800
-#define MPC85xx_PMUXCR_IFC_ADDR24_RES		0x00000C00
-#define MPC85xx_PMUXCR_IFC_PAR_PERR_RES		0x00000300
-#define MPC85xx_PMUXCR_IFC_PAR_PERR_USB		0x00000200
-#define MPC85xx_PMUXCR_LCLK_RES			0x00000040
-#define MPC85xx_PMUXCR_LCLK_USB			0x00000080
-#define MPC85xx_PMUXCR_LCLK_IFC_CS3		0x000000C0
-#define MPC85xx_PMUXCR_SPI_RES			0x00000030
-#define MPC85xx_PMUXCR_SPI_GPIO			0x00000020
-#define MPC85xx_PMUXCR_CAN1_UART		0x00000004
-#define MPC85xx_PMUXCR_CAN1_TDM			0x00000008
-#define MPC85xx_PMUXCR_CAN1_RES			0x0000000C
-#define MPC85xx_PMUXCR_CAN2_UART		0x00000001
-#define MPC85xx_PMUXCR_CAN2_TDM			0x00000002
-#define MPC85xx_PMUXCR_CAN2_RES			0x00000003
+#define MPC85XX_PMUXCR_TSEC1_0_1588		0x40000000
+#define MPC85XX_PMUXCR_TSEC1_0_RES		0xC0000000
+#define MPC85XX_PMUXCR_TSEC1_1_1588_TRIG	0x10000000
+#define MPC85XX_PMUXCR_TSEC1_1_GPIO_12		0x20000000
+#define MPC85XX_PMUXCR_TSEC1_1_RES		0x30000000
+#define MPC85XX_PMUXCR_TSEC1_2_DMA		0x04000000
+#define MPC85XX_PMUXCR_TSEC1_2_GPIO		0x08000000
+#define MPC85XX_PMUXCR_TSEC1_2_RES		0x0C000000
+#define MPC85XX_PMUXCR_TSEC1_3_RES		0x01000000
+#define MPC85XX_PMUXCR_TSEC1_3_GPIO_15		0x02000000
+#define MPC85XX_PMUXCR_IFC_ADDR16_SDHC		0x00400000
+#define MPC85XX_PMUXCR_IFC_ADDR16_USB		0x00800000
+#define MPC85XX_PMUXCR_IFC_ADDR16_IFC_CS2	0x00C00000
+#define MPC85XX_PMUXCR_IFC_ADDR17_18_SDHC	0x00100000
+#define MPC85XX_PMUXCR_IFC_ADDR17_18_USB	0x00200000
+#define MPC85XX_PMUXCR_IFC_ADDR17_18_DMA	0x00300000
+#define MPC85XX_PMUXCR_IFC_ADDR19_SDHC_DATA	0x00040000
+#define MPC85XX_PMUXCR_IFC_ADDR19_USB		0x00080000
+#define MPC85XX_PMUXCR_IFC_ADDR19_DMA		0x000C0000
+#define MPC85XX_PMUXCR_IFC_ADDR20_21_SDHC_DATA	0x00010000
+#define MPC85XX_PMUXCR_IFC_ADDR20_21_USB	0x00020000
+#define MPC85XX_PMUXCR_IFC_ADDR20_21_RES	0x00030000
+#define MPC85XX_PMUXCR_IFC_ADDR22_SDHC		0x00004000
+#define MPC85XX_PMUXCR_IFC_ADDR22_USB		0x00008000
+#define MPC85XX_PMUXCR_IFC_ADDR22_RES		0x0000C000
+#define MPC85XX_PMUXCR_IFC_ADDR23_SDHC		0x00001000
+#define MPC85XX_PMUXCR_IFC_ADDR23_USB		0x00002000
+#define MPC85XX_PMUXCR_IFC_ADDR23_RES		0x00003000
+#define MPC85XX_PMUXCR_IFC_ADDR24_SDHC		0x00000400
+#define MPC85XX_PMUXCR_IFC_ADDR24_USB		0x00000800
+#define MPC85XX_PMUXCR_IFC_ADDR24_RES		0x00000C00
+#define MPC85XX_PMUXCR_IFC_PAR_PERR_RES		0x00000300
+#define MPC85XX_PMUXCR_IFC_PAR_PERR_USB		0x00000200
+#define MPC85XX_PMUXCR_LCLK_RES			0x00000040
+#define MPC85XX_PMUXCR_LCLK_USB			0x00000080
+#define MPC85XX_PMUXCR_LCLK_IFC_CS3		0x000000C0
+#define MPC85XX_PMUXCR_SPI_RES			0x00000030
+#define MPC85XX_PMUXCR_SPI_GPIO			0x00000020
+#define MPC85XX_PMUXCR_CAN1_UART		0x00000004
+#define MPC85XX_PMUXCR_CAN1_TDM			0x00000008
+#define MPC85XX_PMUXCR_CAN1_RES			0x0000000C
+#define MPC85XX_PMUXCR_CAN2_UART		0x00000001
+#define MPC85XX_PMUXCR_CAN2_TDM			0x00000002
+#define MPC85XX_PMUXCR_CAN2_RES			0x00000003
 #endif
 #if defined(CONFIG_ARCH_P1023)
-#define MPC85xx_PMUXCR_TSEC1_1		0x10000000
+#define MPC85XX_PMUXCR_TSEC1_1		0x10000000
 #else
-#define MPC85xx_PMUXCR_SD_DATA		0x80000000
-#define MPC85xx_PMUXCR_SDHC_CD		0x40000000
-#define MPC85xx_PMUXCR_SDHC_WP		0x20000000
-#define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON	0x01000000
-#define MPC85xx_PMUXCR_TDM_ENA		0x00800000
-#define MPC85xx_PMUXCR_QE0		0x00008000
-#define MPC85xx_PMUXCR_QE1		0x00004000
-#define MPC85xx_PMUXCR_QE2		0x00002000
-#define MPC85xx_PMUXCR_QE3		0x00001000
-#define MPC85xx_PMUXCR_QE4		0x00000800
-#define MPC85xx_PMUXCR_QE5		0x00000400
-#define MPC85xx_PMUXCR_QE6		0x00000200
-#define MPC85xx_PMUXCR_QE7		0x00000100
-#define MPC85xx_PMUXCR_QE8		0x00000080
-#define MPC85xx_PMUXCR_QE9		0x00000040
-#define MPC85xx_PMUXCR_QE10		0x00000020
-#define MPC85xx_PMUXCR_QE11		0x00000010
-#define MPC85xx_PMUXCR_QE12		0x00000008
+#define MPC85XX_PMUXCR_SD_DATA		0x80000000
+#define MPC85XX_PMUXCR_SDHC_CD		0x40000000
+#define MPC85XX_PMUXCR_SDHC_WP		0x20000000
+#define MPC85XX_PMUXCR_ELBC_OFF_USB2_ON	0x01000000
+#define MPC85XX_PMUXCR_TDM_ENA		0x00800000
+#define MPC85XX_PMUXCR_QE0		0x00008000
+#define MPC85XX_PMUXCR_QE1		0x00004000
+#define MPC85XX_PMUXCR_QE2		0x00002000
+#define MPC85XX_PMUXCR_QE3		0x00001000
+#define MPC85XX_PMUXCR_QE4		0x00000800
+#define MPC85XX_PMUXCR_QE5		0x00000400
+#define MPC85XX_PMUXCR_QE6		0x00000200
+#define MPC85XX_PMUXCR_QE7		0x00000100
+#define MPC85XX_PMUXCR_QE8		0x00000080
+#define MPC85XX_PMUXCR_QE9		0x00000040
+#define MPC85XX_PMUXCR_QE10		0x00000020
+#define MPC85XX_PMUXCR_QE11		0x00000010
+#define MPC85XX_PMUXCR_QE12		0x00000008
 #endif
 #if defined(CONFIG_ARCH_BSC9131)
-#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ	0x40000000
-#define MPC85xx_PMUXCR_TSEC2_USB		0xC0000000
-#define MPC85xx_PMUXCR_TSEC2_1588_PPS		0x10000000
-#define MPC85xx_PMUXCR_TSEC2_1588_RSVD		0x30000000
-#define MPC85xx_PMUXCR_IFC_AD_GPIO		0x04000000
-#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK		0x0C000000
-#define MPC85xx_PMUXCR_IFC_AD15_GPIO		0x01000000
-#define MPC85xx_PMUXCR_IFC_AD15_TIMER2		0x02000000
-#define MPC85xx_PMUXCR_IFC_AD16_GPO8		0x00400000
-#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0		0x00800000
-#define MPC85xx_PMUXCR_IFC_AD17_GPO		0x00100000
-#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK	0x00300000
-#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP	0x00200000
-#define MPC85xx_PMUXCR_IFC_CS2_GPO65		0x00040000
-#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI		0x00080000
-#define MPC85xx_PMUXCR_SDHC_USIM		0x00010000
-#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK		0x00020000
-#define MPC85xx_PMUXCR_SDHC_GPIO77		0x00030000
-#define MPC85xx_PMUXCR_SDHC_RESV		0x00004000
-#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD		0x00008000
-#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4		0x0000C000
-#define MPC85xx_PMUXCR_USB_CLK_UART_SIN		0x00001000
-#define MPC85xx_PMUXCR_USB_CLK_GPIO69		0x00002000
-#define MPC85xx_PMUXCR_USB_CLK_TIMER3		0x00003000
-#define MPC85xx_PMUXCR_USB_UART_GPIO0		0x00000400
-#define MPC85xx_PMUXCR_USB_RSVD			0x00000C00
-#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN	0x00000800
-#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL	0x00000100
-#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72	0x00000200
-#define MPC85xx_PMUXCR_USB_D1_2_RSVD		0x00000300
-#define MPC85xx_PMUXCR_USB_DIR_GPIO2		0x00000040
-#define MPC85xx_PMUXCR_USB_DIR_TIMER1		0x00000080
-#define MPC85xx_PMUXCR_USB_DIR_MCP_B		0x000000C0
-#define MPC85xx_PMUXCR_SPI1_UART3		0x00000010
-#define MPC85xx_PMUXCR_SPI1_SIM			0x00000020
-#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74	0x00000030
-#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B	0x00000004
-#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen	0x00000008
-#define MPC85xx_PMUXCR_SPI1_CS2_GPO75		0x0000000C
-#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM	0x00000001
-#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen	0x00000002
-#define MPC85xx_PMUXCR_SPI1_CS3_GPO76		0x00000003
+#define MPC85XX_PMUXCR_TSEC2_DMA_GPIO_IRQ	0x40000000
+#define MPC85XX_PMUXCR_TSEC2_USB		0xC0000000
+#define MPC85XX_PMUXCR_TSEC2_1588_PPS		0x10000000
+#define MPC85XX_PMUXCR_TSEC2_1588_RSVD		0x30000000
+#define MPC85XX_PMUXCR_IFC_AD_GPIO		0x04000000
+#define MPC85XX_PMUXCR_IFC_AD_GPIO_MASK		0x0C000000
+#define MPC85XX_PMUXCR_IFC_AD15_GPIO		0x01000000
+#define MPC85XX_PMUXCR_IFC_AD15_TIMER2		0x02000000
+#define MPC85XX_PMUXCR_IFC_AD16_GPO8		0x00400000
+#define MPC85XX_PMUXCR_IFC_AD16_MSRCID0		0x00800000
+#define MPC85XX_PMUXCR_IFC_AD17_GPO		0x00100000
+#define MPC85XX_PMUXCR_IFC_AD17_GPO_MASK	0x00300000
+#define MPC85XX_PMUXCR_IFC_AD17_MSRCID_DSP	0x00200000
+#define MPC85XX_PMUXCR_IFC_CS2_GPO65		0x00040000
+#define MPC85XX_PMUXCR_IFC_CS2_DSP_TDI		0x00080000
+#define MPC85XX_PMUXCR_SDHC_USIM		0x00010000
+#define MPC85XX_PMUXCR_SDHC_TDM_RFS_RCK		0x00020000
+#define MPC85XX_PMUXCR_SDHC_GPIO77		0x00030000
+#define MPC85XX_PMUXCR_SDHC_RESV		0x00004000
+#define MPC85XX_PMUXCR_SDHC_TDM_TXD_RXD		0x00008000
+#define MPC85XX_PMUXCR_SDHC_GPIO_TIMER4		0x0000C000
+#define MPC85XX_PMUXCR_USB_CLK_UART_SIN		0x00001000
+#define MPC85XX_PMUXCR_USB_CLK_GPIO69		0x00002000
+#define MPC85XX_PMUXCR_USB_CLK_TIMER3		0x00003000
+#define MPC85XX_PMUXCR_USB_UART_GPIO0		0x00000400
+#define MPC85XX_PMUXCR_USB_RSVD			0x00000C00
+#define MPC85XX_PMUXCR_USB_GPIO62_TRIG_IN	0x00000800
+#define MPC85XX_PMUXCR_USB_D1_2_IIC2_SDA_SCL	0x00000100
+#define MPC85XX_PMUXCR_USB_D1_2_GPIO71_72	0x00000200
+#define MPC85XX_PMUXCR_USB_D1_2_RSVD		0x00000300
+#define MPC85XX_PMUXCR_USB_DIR_GPIO2		0x00000040
+#define MPC85XX_PMUXCR_USB_DIR_TIMER1		0x00000080
+#define MPC85XX_PMUXCR_USB_DIR_MCP_B		0x000000C0
+#define MPC85XX_PMUXCR_SPI1_UART3		0x00000010
+#define MPC85XX_PMUXCR_SPI1_SIM			0x00000020
+#define MPC85XX_PMUXCR_SPI1_CKSTP_IN_GPO74	0x00000030
+#define MPC85XX_PMUXCR_SPI1_CS2_CKSTP_OUT_B	0x00000004
+#define MPC85XX_PMUXCR_SPI1_CS2_dbg_adi1_rxen	0x00000008
+#define MPC85XX_PMUXCR_SPI1_CS2_GPO75		0x0000000C
+#define MPC85XX_PMUXCR_SPI1_CS3_ANT_TCXO_PWM	0x00000001
+#define MPC85XX_PMUXCR_SPI1_CS3_dbg_adi2_rxen	0x00000002
+#define MPC85XX_PMUXCR_SPI1_CS3_GPO76		0x00000003
 #endif
 #ifdef CONFIG_ARCH_BSC9132
-#define MPC85xx_PMUXCR0_SIM_SEL_MASK	0x0003b000
-#define MPC85xx_PMUXCR0_SIM_SEL		0x00014000
+#define MPC85XX_PMUXCR0_SIM_SEL_MASK	0x0003b000
+#define MPC85XX_PMUXCR0_SIM_SEL		0x00014000
 #endif
 #if defined(CONFIG_ARCH_C29X)
-#define MPC85xx_PMUXCR_SPI_MASK			0x00000300
-#define MPC85xx_PMUXCR_SPI			0x00000000
-#define MPC85xx_PMUXCR_SPI_GPIO			0x00000100
+#define MPC85XX_PMUXCR_SPI_MASK			0x00000300
+#define MPC85XX_PMUXCR_SPI			0x00000000
+#define MPC85XX_PMUXCR_SPI_GPIO			0x00000100
 #endif
 	u32	pmuxcr2;	/* Alt. function signal multiplex control 2 */
 #if defined(CONFIG_ARCH_P1010)
-#define MPC85xx_PMUXCR2_UART_GPIO		0x40000000
-#define MPC85xx_PMUXCR2_UART_TDM		0x80000000
-#define MPC85xx_PMUXCR2_UART_RES		0xC0000000
-#define MPC85xx_PMUXCR2_IRQ2_TRIG_IN		0x10000000
-#define MPC85xx_PMUXCR2_IRQ2_RES		0x30000000
-#define MPC85xx_PMUXCR2_IRQ3_SRESET		0x04000000
-#define MPC85xx_PMUXCR2_IRQ3_RES		0x0C000000
-#define MPC85xx_PMUXCR2_GPIO01_DRVVBUS		0x01000000
-#define MPC85xx_PMUXCR2_GPIO01_RES		0x03000000
-#define MPC85xx_PMUXCR2_GPIO23_CKSTP		0x00400000
-#define MPC85xx_PMUXCR2_GPIO23_RES		0x00800000
-#define MPC85xx_PMUXCR2_GPIO23_USB		0x00C00000
-#define MPC85xx_PMUXCR2_GPIO4_MCP		0x00100000
-#define MPC85xx_PMUXCR2_GPIO4_RES		0x00200000
-#define MPC85xx_PMUXCR2_GPIO4_CLK_OUT		0x00300000
-#define MPC85xx_PMUXCR2_GPIO5_UDE		0x00040000
-#define MPC85xx_PMUXCR2_GPIO5_RES		0x00080000
-#define MPC85xx_PMUXCR2_READY_ASLEEP		0x00020000
-#define MPC85xx_PMUXCR2_DDR_ECC_MUX		0x00010000
-#define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE	0x00008000
-#define MPC85xx_PMUXCR2_POST_EXPOSE		0x00004000
-#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY	0x00002000
-#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE		0x00001000
+#define MPC85XX_PMUXCR2_UART_GPIO		0x40000000
+#define MPC85XX_PMUXCR2_UART_TDM		0x80000000
+#define MPC85XX_PMUXCR2_UART_RES		0xC0000000
+#define MPC85XX_PMUXCR2_IRQ2_TRIG_IN		0x10000000
+#define MPC85XX_PMUXCR2_IRQ2_RES		0x30000000
+#define MPC85XX_PMUXCR2_IRQ3_SRESET		0x04000000
+#define MPC85XX_PMUXCR2_IRQ3_RES		0x0C000000
+#define MPC85XX_PMUXCR2_GPIO01_DRVVBUS		0x01000000
+#define MPC85XX_PMUXCR2_GPIO01_RES		0x03000000
+#define MPC85XX_PMUXCR2_GPIO23_CKSTP		0x00400000
+#define MPC85XX_PMUXCR2_GPIO23_RES		0x00800000
+#define MPC85XX_PMUXCR2_GPIO23_USB		0x00C00000
+#define MPC85XX_PMUXCR2_GPIO4_MCP		0x00100000
+#define MPC85XX_PMUXCR2_GPIO4_RES		0x00200000
+#define MPC85XX_PMUXCR2_GPIO4_CLK_OUT		0x00300000
+#define MPC85XX_PMUXCR2_GPIO5_UDE		0x00040000
+#define MPC85XX_PMUXCR2_GPIO5_RES		0x00080000
+#define MPC85XX_PMUXCR2_READY_ASLEEP		0x00020000
+#define MPC85XX_PMUXCR2_DDR_ECC_MUX		0x00010000
+#define MPC85XX_PMUXCR2_DEBUG_PORT_EXPOSE	0x00008000
+#define MPC85XX_PMUXCR2_POST_EXPOSE		0x00004000
+#define MPC85XX_PMUXCR2_DEBUG_MUX_SEL_USBPHY	0x00002000
+#define MPC85XX_PMUXCR2_PLL_LKDT_EXPOSE		0x00001000
 #endif
 #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
 #if defined(CONFIG_ARCH_BSC9131)
-#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD		0X40000000
-#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS		0X80000000
-#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42		0xC0000000
-#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2		0x10000000
-#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK		0x20000000
-#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43		0x30000000
-#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD		0x04000000
-#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B		0x08000000
-#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44		0x0C000000
-#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED		0x01000000
-#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD		0x02000000
-#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45		0x03000000
-#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP			0x00400000
-#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B		0x00800000
-#define MPC85xx_PMUXCR2_ANT1_TIMER5			0x00100000
-#define MPC85xx_PMUXCR2_ANT1_TSEC_1588			0x00200000
-#define MPC85xx_PMUXCR2_ANT1_GPIO95_19			0x00300000
-#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK	0x00040000
-#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD		0x00080000
-#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20	0x000C0000
-#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0		0x00010000
-#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3		0x00020000
-#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84		0x00030000
-#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4		0x00004000
-#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7		0x00008000
-#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88		0x0000C000
-#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK		0x00001000
-#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9		0x00002000
-#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22		0x00003000
-#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7		0x00000400
-#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11	0x00000800
-#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24		0x00000C00
-#define MPC85xx_PMUXCR2_ANT2_RSVD			0x00000100
-#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA		0x00000300
-#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB		0x00000040
-#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO	0x000000C0
-#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD			0x00000010
-#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8		0x00000020
-#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61		0x00000030
-#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53			0x00000004
-#define MPC85xx_PMUXCR2_ANT3_DO_TDM			0x00000001
-#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49		0x00000002
+#define MPC85XX_PMUXCR2_UART_CTS_B0_SIM_PD		0X40000000
+#define MPC85XX_PMUXCR2_UART_CTS_B0_DSP_TMS		0X80000000
+#define MPC85XX_PMUXCR2_UART_CTS_B0_GPIO42		0xC0000000
+#define MPC85XX_PMUXCR2_UART_RTS_B0_PWM2		0x10000000
+#define MPC85XX_PMUXCR2_UART_RTS_B0_DSP_TCK		0x20000000
+#define MPC85XX_PMUXCR2_UART_RTS_B0_GPIO43		0x30000000
+#define MPC85XX_PMUXCR2_UART_CTS_B1_SIM_PD		0x04000000
+#define MPC85XX_PMUXCR2_UART_CTS_B1_SRESET_B		0x08000000
+#define MPC85XX_PMUXCR2_UART_CTS_B1_GPIO44		0x0C000000
+#define MPC85XX_PMUXCR2_UART_RTS_B1_PPS_LED		0x01000000
+#define MPC85XX_PMUXCR2_UART_RTS_B1_RSVD		0x02000000
+#define MPC85XX_PMUXCR2_UART_RTS_B1_GPIO45		0x03000000
+#define MPC85XX_PMUXCR2_TRIG_OUT_ASLEEP			0x00400000
+#define MPC85XX_PMUXCR2_TRIG_OUT_DSP_TRST_B		0x00800000
+#define MPC85XX_PMUXCR2_ANT1_TIMER5			0x00100000
+#define MPC85XX_PMUXCR2_ANT1_TSEC_1588			0x00200000
+#define MPC85XX_PMUXCR2_ANT1_GPIO95_19			0x00300000
+#define MPC85XX_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK	0x00040000
+#define MPC85XX_PMUXCR2_ANT1_TX_RX_FRAME_RSVD		0x00080000
+#define MPC85XX_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20	0x000C0000
+#define MPC85XX_PMUXCR2_ANT1_DIO0_3_SPI3_CS0		0x00010000
+#define MPC85XX_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3		0x00020000
+#define MPC85XX_PMUXCR2_ANT1_DIO0_3_GPIO81_84		0x00030000
+#define MPC85XX_PMUXCR2_ANT1_DIO4_7_SPI4		0x00004000
+#define MPC85XX_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7		0x00008000
+#define MPC85XX_PMUXCR2_ANT1_DIO4_7_GPIO85_88		0x0000C000
+#define MPC85XX_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK		0x00001000
+#define MPC85XX_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9		0x00002000
+#define MPC85XX_PMUXCR2_ANT1_DIO8_9_GPIO21_22		0x00003000
+#define MPC85XX_PMUXCR2_ANT1_DIO10_11_TIMER6_7		0x00000400
+#define MPC85XX_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11	0x00000800
+#define MPC85XX_PMUXCR2_ANT1_DIO10_11_GPIO23_24		0x00000C00
+#define MPC85XX_PMUXCR2_ANT2_RSVD			0x00000100
+#define MPC85XX_PMUXCR2_ANT2_GPO90_91_DMA		0x00000300
+#define MPC85XX_PMUXCR2_ANT2_ENABLE_DIO0_10_USB		0x00000040
+#define MPC85XX_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO	0x000000C0
+#define MPC85XX_PMUXCR2_ANT2_DIO11_RSVD			0x00000010
+#define MPC85XX_PMUXCR2_ANT2_DIO11_TIMER8		0x00000020
+#define MPC85XX_PMUXCR2_ANT2_DIO11_GPIO61		0x00000030
+#define MPC85XX_PMUXCR2_ANT3_AGC_GPO53			0x00000004
+#define MPC85XX_PMUXCR2_ANT3_DO_TDM			0x00000001
+#define MPC85XX_PMUXCR2_ANT3_DO_GPIO46_49		0x00000002
 #endif
 	u32	pmuxcr3;
 #if defined(CONFIG_ARCH_BSC9131)
-#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM			0x40000000
-#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51		0x80000000
-#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B	0x10000000
-#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53		0x20000000
-#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B			0x04000000
-#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54			0x08000000
-#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT	0x01000000
-#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56		0x02000000
-#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT		0x00400000
-#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57		0x00800000
-#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93			0x00100000
-#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94			0x00040000
-#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD			0x00010000
-#define MPC85xx_PMUXCR3_ANT2_GPO89			0x00030000
+#define MPC85XX_PMUXCR3_ANT3_DO4_5_TDM			0x40000000
+#define MPC85XX_PMUXCR3_ANT3_DO4_5_GPIO_50_51		0x80000000
+#define MPC85XX_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B	0x10000000
+#define MPC85XX_PMUXCR3_ANT3_DO6_7_GPIO_52_53		0x20000000
+#define MPC85XX_PMUXCR3_ANT3_DO8_MCP_B			0x04000000
+#define MPC85XX_PMUXCR3_ANT3_DO8_GPIO54			0x08000000
+#define MPC85XX_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT	0x01000000
+#define MPC85XX_PMUXCR3_ANT3_DO9_10_GPIO55_56		0x02000000
+#define MPC85XX_PMUXCR3_ANT3_DO11_IRQ_OUT		0x00400000
+#define MPC85XX_PMUXCR3_ANT3_DO11_GPIO57		0x00800000
+#define MPC85XX_PMUXCR3_SPI2_CS2_GPO93			0x00100000
+#define MPC85XX_PMUXCR3_SPI2_CS3_GPO94			0x00040000
+#define MPC85XX_PMUXCR3_ANT2_AGC_RSVD			0x00010000
+#define MPC85XX_PMUXCR3_ANT2_GPO89			0x00030000
 #endif
 #ifdef CONFIG_ARCH_BSC9132
-#define MPC85xx_PMUXCR3_USB_SEL_MASK	0x0000ff00
-#define MPC85xx_PMUXCR3_UART2_SEL	0x00005000
-#define MPC85xx_PMUXCR3_UART3_SEL_MASK	0xc0000000
-#define MPC85xx_PMUXCR3_UART3_SEL	0x40000000
+#define MPC85XX_PMUXCR3_USB_SEL_MASK	0x0000ff00
+#define MPC85XX_PMUXCR3_UART2_SEL	0x00005000
+#define MPC85XX_PMUXCR3_UART3_SEL_MASK	0xc0000000
+#define MPC85XX_PMUXCR3_UART3_SEL	0x40000000
 #endif
 	u32 pmuxcr4;
 #else
 	u8	res6[8];
 #endif
 	u32	devdisr;	/* Device disable control */
-#define MPC85xx_DEVDISR_PCI1		0x80000000
-#define MPC85xx_DEVDISR_PCI2		0x40000000
-#define MPC85xx_DEVDISR_PCIE		0x20000000
-#define MPC85xx_DEVDISR_LBC		0x08000000
-#define MPC85xx_DEVDISR_PCIE2		0x04000000
-#define MPC85xx_DEVDISR_PCIE3		0x02000000
-#define MPC85xx_DEVDISR_SEC		0x01000000
-#define MPC85xx_DEVDISR_SRIO		0x00080000
-#define MPC85xx_DEVDISR_RMSG		0x00040000
-#define MPC85xx_DEVDISR_DDR		0x00010000
-#define MPC85xx_DEVDISR_CPU		0x00008000
-#define MPC85xx_DEVDISR_CPU0		MPC85xx_DEVDISR_CPU
-#define MPC85xx_DEVDISR_TB		0x00004000
-#define MPC85xx_DEVDISR_TB0		MPC85xx_DEVDISR_TB
-#define MPC85xx_DEVDISR_CPU1		0x00002000
-#define MPC85xx_DEVDISR_TB1		0x00001000
-#define MPC85xx_DEVDISR_DMA		0x00000400
-#define MPC85xx_DEVDISR_TSEC1		0x00000080
-#define MPC85xx_DEVDISR_TSEC2		0x00000040
-#define MPC85xx_DEVDISR_TSEC3		0x00000020
-#define MPC85xx_DEVDISR_TSEC4		0x00000010
-#define MPC85xx_DEVDISR_I2C		0x00000004
-#define MPC85xx_DEVDISR_DUART		0x00000002
+#define MPC85XX_DEVDISR_PCI1		0x80000000
+#define MPC85XX_DEVDISR_PCI2		0x40000000
+#define MPC85XX_DEVDISR_PCIE		0x20000000
+#define MPC85XX_DEVDISR_LBC		0x08000000
+#define MPC85XX_DEVDISR_PCIE2		0x04000000
+#define MPC85XX_DEVDISR_PCIE3		0x02000000
+#define MPC85XX_DEVDISR_SEC		0x01000000
+#define MPC85XX_DEVDISR_SRIO		0x00080000
+#define MPC85XX_DEVDISR_RMSG		0x00040000
+#define MPC85XX_DEVDISR_DDR		0x00010000
+#define MPC85XX_DEVDISR_CPU		0x00008000
+#define MPC85XX_DEVDISR_CPU0		MPC85XX_DEVDISR_CPU
+#define MPC85XX_DEVDISR_TB		0x00004000
+#define MPC85XX_DEVDISR_TB0		MPC85XX_DEVDISR_TB
+#define MPC85XX_DEVDISR_CPU1		0x00002000
+#define MPC85XX_DEVDISR_TB1		0x00001000
+#define MPC85XX_DEVDISR_DMA		0x00000400
+#define MPC85XX_DEVDISR_TSEC1		0x00000080
+#define MPC85XX_DEVDISR_TSEC2		0x00000040
+#define MPC85XX_DEVDISR_TSEC3		0x00000020
+#define MPC85XX_DEVDISR_TSEC4		0x00000010
+#define MPC85XX_DEVDISR_I2C		0x00000004
+#define MPC85XX_DEVDISR_DUART		0x00000002
 	u8	res7[12];
 	u32	powmgtcsr;	/* Power management status & control */
 	u8	res8[12];
@@ -2457,36 +2457,36 @@ struct ccsr_pman {
 #define CFG_SYS_FSL_CPC_OFFSET		0x10000
 #define CFG_SYS_FSL_SCFG_OFFSET		0xFC000
 #define CFG_SYS_FSL_PAMU_OFFSET		0x20000
-#define CFG_SYS_MPC85xx_DMA1_OFFSET		0x100000
-#define CFG_SYS_MPC85xx_DMA2_OFFSET		0x101000
-#define CFG_SYS_MPC85xx_DMA3_OFFSET		0x102000
-#define CFG_SYS_MPC85xx_DMA_OFFSET		CFG_SYS_MPC85xx_DMA1_OFFSET
-#define CFG_SYS_MPC85xx_ESPI_OFFSET		0x110000
-#define CFG_SYS_MPC85xx_ESDHC_OFFSET		0x114000
-#define CFG_SYS_MPC85xx_LBC_OFFSET		0x124000
-#define CFG_SYS_MPC85xx_IFC_OFFSET		0x124000
-#define CFG_SYS_MPC85xx_GPIO_OFFSET		0x130000
-#define CFG_SYS_MPC85xx_TDM_OFFSET		0x185000
-#define CFG_SYS_MPC85xx_QE_OFFSET		0x140000
+#define CFG_SYS_MPC85XX_DMA1_OFFSET		0x100000
+#define CFG_SYS_MPC85XX_DMA2_OFFSET		0x101000
+#define CFG_SYS_MPC85XX_DMA3_OFFSET		0x102000
+#define CFG_SYS_MPC85XX_DMA_OFFSET		CFG_SYS_MPC85XX_DMA1_OFFSET
+#define CFG_SYS_MPC85XX_ESPI_OFFSET		0x110000
+#define CFG_SYS_MPC85XX_ESDHC_OFFSET		0x114000
+#define CFG_SYS_MPC85XX_LBC_OFFSET		0x124000
+#define CFG_SYS_MPC85XX_IFC_OFFSET		0x124000
+#define CFG_SYS_MPC85XX_GPIO_OFFSET		0x130000
+#define CFG_SYS_MPC85XX_TDM_OFFSET		0x185000
+#define CFG_SYS_MPC85XX_QE_OFFSET		0x140000
 #define CFG_SYS_FSL_CORENET_RMAN_OFFSET	0x1e0000
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
 	!defined(CONFIG_ARCH_B4420)
-#define CFG_SYS_MPC85xx_PCIE1_OFFSET		0x240000
-#define CFG_SYS_MPC85xx_PCIE2_OFFSET		0x250000
-#define CFG_SYS_MPC85xx_PCIE3_OFFSET		0x260000
-#define CFG_SYS_MPC85xx_PCIE4_OFFSET		0x270000
+#define CFG_SYS_MPC85XX_PCIE1_OFFSET		0x240000
+#define CFG_SYS_MPC85XX_PCIE2_OFFSET		0x250000
+#define CFG_SYS_MPC85XX_PCIE3_OFFSET		0x260000
+#define CFG_SYS_MPC85XX_PCIE4_OFFSET		0x270000
 #else
-#define CFG_SYS_MPC85xx_PCIE1_OFFSET		0x200000
-#define CFG_SYS_MPC85xx_PCIE2_OFFSET		0x201000
-#define CFG_SYS_MPC85xx_PCIE3_OFFSET		0x202000
-#define CFG_SYS_MPC85xx_PCIE4_OFFSET		0x203000
+#define CFG_SYS_MPC85XX_PCIE1_OFFSET		0x200000
+#define CFG_SYS_MPC85XX_PCIE2_OFFSET		0x201000
+#define CFG_SYS_MPC85XX_PCIE3_OFFSET		0x202000
+#define CFG_SYS_MPC85XX_PCIE4_OFFSET		0x203000
 #endif
-#define CFG_SYS_MPC85xx_USB1_OFFSET		0x210000
-#define CFG_SYS_MPC85xx_USB2_OFFSET		0x211000
-#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
-#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
-#define CFG_SYS_MPC85xx_SATA1_OFFSET		0x220000
-#define CFG_SYS_MPC85xx_SATA2_OFFSET		0x221000
+#define CFG_SYS_MPC85XX_USB1_OFFSET		0x210000
+#define CFG_SYS_MPC85XX_USB2_OFFSET		0x211000
+#define CFG_SYS_MPC85XX_USB1_PHY_OFFSET 0x214000
+#define CFG_SYS_MPC85XX_USB2_PHY_OFFSET 0x214100
+#define CFG_SYS_MPC85XX_SATA1_OFFSET		0x220000
+#define CFG_SYS_MPC85XX_SATA2_OFFSET		0x221000
 #define CFG_SYS_FSL_SEC_OFFSET		0x300000
 #define CFG_SYS_FSL_JR0_OFFSET		0x301000
 #define CFG_SYS_SEC_MON_OFFSET		0x314000
@@ -2515,34 +2515,34 @@ struct ccsr_pman {
 #define CFG_SYS_FSL_FM2_RX1_10G_OFFSET	0x591000
 #define CFG_SYS_FSL_CLUSTER_1_L2_OFFSET	0xC20000
 #else
-#define CFG_SYS_MPC85xx_ECM_OFFSET		0x0000
+#define CFG_SYS_MPC85XX_ECM_OFFSET		0x0000
 #define CFG_SYS_MPC8xxx_DDR_OFFSET		0x2000
-#define CFG_SYS_MPC85xx_LBC_OFFSET		0x5000
+#define CFG_SYS_MPC85XX_LBC_OFFSET		0x5000
 #define CFG_SYS_MPC8xxx_DDR2_OFFSET		0x6000
-#define CFG_SYS_MPC85xx_ESPI_OFFSET		0x7000
-#define CFG_SYS_MPC85xx_PCI1_OFFSET		0x8000
-#define CFG_SYS_MPC85xx_PCIX_OFFSET		0x8000
-#define CFG_SYS_MPC85xx_PCI2_OFFSET		0x9000
-#define CFG_SYS_MPC85xx_PCIX2_OFFSET		0x9000
-#define CFG_SYS_MPC85xx_PCIE1_OFFSET         0xa000
-#define CFG_SYS_MPC85xx_PCIE2_OFFSET         0x9000
+#define CFG_SYS_MPC85XX_ESPI_OFFSET		0x7000
+#define CFG_SYS_MPC85XX_PCI1_OFFSET		0x8000
+#define CFG_SYS_MPC85XX_PCIX_OFFSET		0x8000
+#define CFG_SYS_MPC85XX_PCI2_OFFSET		0x9000
+#define CFG_SYS_MPC85XX_PCIX2_OFFSET		0x9000
+#define CFG_SYS_MPC85XX_PCIE1_OFFSET         0xa000
+#define CFG_SYS_MPC85XX_PCIE2_OFFSET         0x9000
 #if defined(CONFIG_ARCH_P2020)
-#define CFG_SYS_MPC85xx_PCIE3_OFFSET         0x8000
+#define CFG_SYS_MPC85XX_PCIE3_OFFSET         0x8000
 #else
-#define CFG_SYS_MPC85xx_PCIE3_OFFSET         0xb000
+#define CFG_SYS_MPC85XX_PCIE3_OFFSET         0xb000
 #endif
-#define CFG_SYS_MPC85xx_GPIO_OFFSET		0xF000
-#define CFG_SYS_MPC85xx_SATA1_OFFSET		0x18000
-#define CFG_SYS_MPC85xx_SATA2_OFFSET		0x19000
-#define CFG_SYS_MPC85xx_IFC_OFFSET		0x1e000
-#define CFG_SYS_MPC85xx_L2_OFFSET		0x20000
-#define CFG_SYS_MPC85xx_DMA_OFFSET		0x21000
-#define CFG_SYS_MPC85xx_USB1_OFFSET		0x22000
-#define CFG_SYS_MPC85xx_USB2_OFFSET		0x23000
-#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET	0xE5000
-#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET	0xE5100
+#define CFG_SYS_MPC85XX_GPIO_OFFSET		0xF000
+#define CFG_SYS_MPC85XX_SATA1_OFFSET		0x18000
+#define CFG_SYS_MPC85XX_SATA2_OFFSET		0x19000
+#define CFG_SYS_MPC85XX_IFC_OFFSET		0x1e000
+#define CFG_SYS_MPC85XX_L2_OFFSET		0x20000
+#define CFG_SYS_MPC85XX_DMA_OFFSET		0x21000
+#define CFG_SYS_MPC85XX_USB1_OFFSET		0x22000
+#define CFG_SYS_MPC85XX_USB2_OFFSET		0x23000
+#define CFG_SYS_MPC85XX_USB1_PHY_OFFSET	0xE5000
+#define CFG_SYS_MPC85XX_USB2_PHY_OFFSET	0xE5100
 #define CFG_SYS_MDIO1_OFFSET			0x24000
-#define CFG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
+#define CFG_SYS_MPC85XX_ESDHC_OFFSET		0x2e000
 #if defined(CONFIG_ARCH_C29X)
 #define CFG_SYS_FSL_SEC_OFFSET		0x80000
 #define CFG_SYS_FSL_JR0_OFFSET               0x81000
@@ -2550,8 +2550,8 @@ struct ccsr_pman {
 #define CFG_SYS_FSL_SEC_OFFSET		0x30000
 #define CFG_SYS_FSL_JR0_OFFSET               0x31000
 #endif
-#define CFG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
-#define CFG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
+#define CFG_SYS_MPC85XX_SERDES2_OFFSET	0xE3100
+#define CFG_SYS_MPC85XX_SERDES1_OFFSET	0xE3000
 #define CFG_SYS_SEC_MON_OFFSET		0xE6000
 #define CFG_SYS_SFP_OFFSET			0xE7000
 #define CFG_SYS_FSL_QMAN_OFFSET		0x88000
@@ -2562,8 +2562,8 @@ struct ccsr_pman {
 #define CFG_SYS_FSL_FM1_DTSEC1_OFFSET	0x1e0000
 #endif
 
-#define CFG_SYS_MPC85xx_PIC_OFFSET		0x40000
-#define CFG_SYS_MPC85xx_GUTS_OFFSET		0xE0000
+#define CFG_SYS_MPC85XX_PIC_OFFSET		0x40000
+#define CFG_SYS_MPC85XX_GUTS_OFFSET		0xE0000
 #define CFG_SYS_FSL_SRIO_OFFSET		0xC0000
 
 #define CFG_SYS_FSL_CPC_ADDR	\
@@ -2580,16 +2580,16 @@ struct ccsr_pman {
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_RAID_ENGINE_OFFSET)
 #define CFG_SYS_FSL_CORENET_RMAN_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RMAN_OFFSET)
-#define CFG_SYS_MPC85xx_GUTS_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GUTS_OFFSET)
+#define CFG_SYS_MPC85XX_GUTS_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_GUTS_OFFSET)
 #define CFG_SYS_FSL_CORENET_CCM_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CCM_OFFSET)
 #define CFG_SYS_FSL_CORENET_CLK_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CLK_OFFSET)
 #define CFG_SYS_FSL_CORENET_RCPM_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RCPM_OFFSET)
-#define CFG_SYS_MPC85xx_ECM_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ECM_OFFSET)
+#define CFG_SYS_MPC85XX_ECM_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_ECM_OFFSET)
 #define CFG_SYS_FSL_DDR_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
 #define CFG_SYS_FSL_DDR2_ADDR \
@@ -2597,33 +2597,33 @@ struct ccsr_pman {
 #define CFG_SYS_FSL_DDR3_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET)
 #define CFG_SYS_LBC_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_LBC_OFFSET)
 #define CFG_SYS_IFC_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_IFC_OFFSET)
-#define CFG_SYS_MPC85xx_ESPI_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESPI_OFFSET)
-#define CFG_SYS_MPC85xx_PCIX_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX_OFFSET)
-#define CFG_SYS_MPC85xx_PCIX2_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX2_OFFSET)
-#define CFG_SYS_MPC85xx_GPIO_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GPIO_OFFSET)
-#define CFG_SYS_MPC85xx_SATA1_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA1_OFFSET)
-#define CFG_SYS_MPC85xx_SATA2_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA2_OFFSET)
-#define CFG_SYS_MPC85xx_L2_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_L2_OFFSET)
-#define CFG_SYS_MPC85xx_DMA_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_DMA_OFFSET)
-#define CFG_SYS_MPC85xx_ESDHC_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESDHC_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_IFC_OFFSET)
+#define CFG_SYS_MPC85XX_ESPI_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_ESPI_OFFSET)
+#define CFG_SYS_MPC85XX_PCIX_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_PCIX_OFFSET)
+#define CFG_SYS_MPC85XX_PCIX2_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_PCIX2_OFFSET)
+#define CFG_SYS_MPC85XX_GPIO_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_GPIO_OFFSET)
+#define CFG_SYS_MPC85XX_SATA1_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_SATA1_OFFSET)
+#define CFG_SYS_MPC85XX_SATA2_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_SATA2_OFFSET)
+#define CFG_SYS_MPC85XX_L2_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_L2_OFFSET)
+#define CFG_SYS_MPC85XX_DMA_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_DMA_OFFSET)
+#define CFG_SYS_MPC85XX_ESDHC_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_ESDHC_OFFSET)
 #define CFG_SYS_MPC8xxx_PIC_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PIC_OFFSET)
-#define CFG_SYS_MPC85xx_SERDES1_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES1_OFFSET)
-#define CFG_SYS_MPC85xx_SERDES2_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES2_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_PIC_OFFSET)
+#define CFG_SYS_MPC85XX_SERDES1_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_SERDES1_OFFSET)
+#define CFG_SYS_MPC85XX_SERDES2_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_SERDES2_OFFSET)
 #define CFG_SYS_FSL_CORENET_SERDES_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES_OFFSET)
 #define CFG_SYS_FSL_CORENET_SERDES2_ADDR \
@@ -2632,14 +2632,14 @@ struct ccsr_pman {
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES3_OFFSET)
 #define CFG_SYS_FSL_CORENET_SERDES4_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES4_OFFSET)
-#define CFG_SYS_MPC85xx_USB1_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_OFFSET)
-#define CFG_SYS_MPC85xx_USB2_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_OFFSET)
-#define CFG_SYS_MPC85xx_USB1_PHY_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_PHY_OFFSET)
-#define CFG_SYS_MPC85xx_USB2_PHY_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_PHY_OFFSET)
+#define CFG_SYS_MPC85XX_USB1_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_USB1_OFFSET)
+#define CFG_SYS_MPC85XX_USB2_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_USB2_OFFSET)
+#define CFG_SYS_MPC85XX_USB1_PHY_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_USB1_PHY_OFFSET)
+#define CFG_SYS_MPC85XX_USB2_PHY_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_USB2_PHY_OFFSET)
 #define CFG_SYS_FSL_SEC_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
 #define CFG_SYS_FSL_JR0_ADDR \
@@ -2656,9 +2656,9 @@ struct ccsr_pman {
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET)
 
 #define CFG_SYS_PCIE1_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_PCIE1_OFFSET)
 #define CFG_SYS_PCIE2_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_PCIE2_OFFSET)
 
 #define CFG_SYS_SFP_ADDR  \
 	(CONFIG_SYS_IMMR + CFG_SYS_SFP_OFFSET)
@@ -2736,9 +2736,9 @@ struct dcsr_dcfg_regs {
 	u8  res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
 };
 
-#define CFG_SYS_MPC85xx_SCFG \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SCFG_OFFSET)
-#define CFG_SYS_MPC85xx_SCFG_OFFSET	0xfc000
+#define CFG_SYS_MPC85XX_SCFG \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_SCFG_OFFSET)
+#define CFG_SYS_MPC85XX_SCFG_OFFSET	0xfc000
 /* The supplement configuration unit register */
 struct ccsr_scfg {
 	u32 dpslpcr;	/* 0x000 Deep Sleep Control register */
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h
index 0ed6beca387..2643eec7820 100644
--- a/arch/powerpc/include/asm/mpc85xx_gpio.h
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -20,7 +20,7 @@
 static inline void mpc85xx_gpio_set(unsigned int mask,
 		unsigned int dir, unsigned int val)
 {
-	ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
+	ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR);
 
 	/* First mask off the unwanted parts of "dir" and "val" */
 	dir &= mask;
@@ -56,7 +56,7 @@ static inline void mpc85xx_gpio_set_high(unsigned int gpios)
 
 static inline unsigned int mpc85xx_gpio_get(unsigned int mask)
 {
-	ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
+	ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR);
 
 	/* Read the requested values */
 	return in_be32(&gpio->gpdat) & mask;
diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h
index 3b13f7ff166..708cd3920cc 100644
--- a/arch/powerpc/include/asm/ppc.h
+++ b/arch/powerpc/include/asm/ppc.h
@@ -15,7 +15,7 @@
 #if defined(CONFIG_MPC8xx)
 #include <asm/immap_8xx.h>
 #endif
-#ifdef CONFIG_MPC85xx
+#ifdef CONFIG_MPC85XX
 #include <mpc85xx.h>
 #include <asm/immap_85xx.h>
 #endif
@@ -50,7 +50,7 @@ static inline uint get_svr(void)
 	return mfspr(SVR);
 }
 
-#if defined(CONFIG_MPC85xx)	|| \
+#if defined(CONFIG_MPC85XX)	|| \
 	defined(CONFIG_MPC86xx)	|| \
 	defined(CONFIG_MPC83XX)
 unsigned char	in8(unsigned int);
@@ -78,8 +78,8 @@ void ddr_enable_ecc(unsigned int dram_size);
 #endif
 #endif
 
-#if defined(CONFIG_MPC85xx)
-typedef MPC85xx_SYS_INFO sys_info_t;
+#if defined(CONFIG_MPC85XX)
+typedef MPC85XX_SYS_INFO sys_info_t;
 void get_sys_info(sys_info_t *);
 void ft_fixup_cpu(void *, u64);
 void ft_fixup_num_cores(void *);
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index d80b7d75563..2bb2af2cb64 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -750,7 +750,7 @@
 #define MAS7	SPRN_MAS7
 #define MAS8	SPRN_MAS8
 
-#if defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC85XX)
 #define DAR_DEAR DEAR
 #else
 #define DAR_DEAR DAR
@@ -1001,7 +1001,7 @@
 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC w/o E bit*/
 
 /* whether MPC8xxxE (i.e. has SEC) */
-#if defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC85XX)
 #define IS_E_PROCESSOR(svr)	(svr & 0x80000)
 #else
 #if defined(CONFIG_MPC83XX)
@@ -1156,7 +1156,7 @@ int fixup_cpu(void);
 int fsl_qoriq_core_to_cluster(unsigned int core);
 int fsl_qoriq_dsp_core_to_cluster(unsigned int core);
 
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx)
 #define CPU_TYPE_ENTRY(n, v, nc) \
 	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), \
 	  .mask = (1 << (nc)) - 1 }
@@ -1176,7 +1176,7 @@ int prt_83xx_rsr(void);
 
 #endif /* ndef ASSEMBLY*/
 
-#if defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC85XX)
  #define EPAPR_MAGIC	(0x45504150)
 #else
  #define EPAPR_MAGIC	(0x65504150)
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 7b392b06bcb..e5324bf8fc1 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -290,7 +290,7 @@ void boot_prep_vxworks(struct bootm_headers *images)
 		fdt_fixup_memory(images->ft_addr, base, size);
 
 #if defined(CONFIG_MP)
-#if defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC85XX)
 	ft_fixup_cpu(images->ft_addr, base + size);
 	ft_fixup_num_cores(images->ft_addr);
 #elif defined(CONFIG_MPC86xx)
diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S
index e55025181f7..472548d494d 100644
--- a/arch/powerpc/lib/ppccache.S
+++ b/arch/powerpc/lib/ppccache.S
@@ -64,7 +64,7 @@ ppcSync:
  * flush_dcache_range(unsigned long start, unsigned long stop)
  */
 _GLOBAL(flush_dcache_range)
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx)
 	li	r5,L1_CACHE_BYTES-1
 	andc	r3,r3,r5
 	subf	r4,r3,r4
@@ -88,7 +88,7 @@ _GLOBAL(flush_dcache_range)
  * invalidate_dcache_range(unsigned long start, unsigned long stop)
  */
 _GLOBAL(invalidate_dcache_range)
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx)
 	li	r5,L1_CACHE_BYTES-1
 	andc	r3,r3,r5
 	subf	r4,r3,r4
diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index b47ce052516..fa71abad231 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -27,8 +27,8 @@
 #include <asm/arch/immap_ls102xa.h>
 #endif
 
-#if defined(CONFIG_MPC85xx)
-#define CFG_DCFG_ADDR	CFG_SYS_MPC85xx_GUTS_ADDR
+#if defined(CONFIG_MPC85XX)
+#define CFG_DCFG_ADDR	CFG_SYS_MPC85XX_GUTS_ADDR
 #else
 #define CFG_DCFG_ADDR	CFG_SYS_FSL_GUTS_ADDR
 #endif
@@ -50,17 +50,17 @@ int fsl_check_boot_mode_secure(void)
 	if (val == ITS_MASK)
 		return 1;
 
-#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx)
+#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85XX)
 	/* For PBL based platforms check the SB_EN bit in RCWSR */
 	val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK;
 	if (val == RCW_SB_EN_MASK)
 		return 1;
 #endif
 
-#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET)
+#if defined(CONFIG_MPC85XX) && !defined(CONFIG_FSL_CORENET)
 	/* For Non-PBL Platforms, check the Device Status register 2*/
-	val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK;
-	if (val != MPC85xx_PORDEVSR2_SBC_MASK)
+	val = gur_in32(&gur->pordevsr2) & MPC85XX_PORDEVSR2_SBC_MASK;
+	if (val != MPC85XX_PORDEVSR2_SBC_MASK)
 		return 1;
 
 #endif
diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index bfe6357b0d6..451341ddc04 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -73,17 +73,17 @@ static u32 check_ie(struct fsl_secboot_img_priv *img)
 }
 
 /* This function returns the CSF Header Address of uboot
- * For MPC85xx based platforms, the LAW mapping for NOR
+ * For MPC85XX based platforms, the LAW mapping for NOR
  * flash changes in uboot code. Hence the offset needs
  * to be calculated and added to the new NOR flash base
  * address
  */
-#if defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC85XX)
 #include <flash.h>
 
 int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
 	u32 csf_flash_offset = csf_hdr_addr & ~(CFG_SYS_PBI_FLASH_BASE);
 	u32 flash_addr, addr;
@@ -168,7 +168,7 @@ static int get_ie_info_addr(uintptr_t *ie_addr)
 #endif
 
 	/* IE Key Table is the first entry in the SG Table */
-#if defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC85XX)
 	*ie_addr = (uintptr_t)((sg_tbl->src_addr &
 			~(CFG_SYS_PBI_FLASH_BASE)) +
 			flash_base_addr);
diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c
index d3323b9ec1e..6d05935bf97 100644
--- a/board/freescale/common/mpc85xx_sleep.c
+++ b/board/freescale/common/mpc85xx_sleep.c
@@ -24,7 +24,7 @@ void __weak board_sleep_prepare(void)
 
 bool is_warm_boot(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
+	struct ccsr_gur __iomem *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
 
 	if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR)
 		return 1;
@@ -46,7 +46,7 @@ static void dp_ddr_restore(void)
 {
 	u64 *src, *dst;
 	int i;
-	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85xx_SCFG;
+	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85XX_SCFG;
 
 	/* get the address of ddr date from SPARECR3 */
 	src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8);
@@ -80,7 +80,7 @@ int fsl_dp_resume(void)
 {
 	u32 start_addr;
 	void (*kernel_resume)(void);
-	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85xx_SCFG;
+	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85XX_SCFG;
 
 	if (!is_warm_boot())
 		return 0;
diff --git a/board/freescale/common/via.h b/board/freescale/common/via.h
index 77cfacc5261..7f2f64668d2 100644
--- a/board/freescale/common/via.h
+++ b/board/freescale/common/via.h
@@ -1,4 +1,4 @@
-#ifndef _MPC85xx_VIA_H
+#ifndef _MPC85XX_VIA_H
 void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
 
 /* Function 1, IDE */
@@ -15,4 +15,4 @@ void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct
 
 /* Function 6, AC97 Interface */
 void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
-#endif /* _MPC85xx_VIA_H */
+#endif /* _MPC85XX_VIA_H */
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 5ec3f2a76b1..f35ec9902b6 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -542,7 +542,7 @@ int adjust_vdd(ulong vdd_override)
 	struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 #else
 	ccsr_gur_t __iomem *gur =
-		(void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+		(void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 #endif
 	u8 vid;
 	u32 fusesr;
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index ec6e3a2d0ab..48f9f6bbc62 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -33,8 +33,8 @@ void local_bus_init(void);
 
 int checkboard (void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85XX_ECM_ADDR);
 
 	/* PCI slot in USER bits CSR[6:7] by convention. */
 	uint pci_slot = get_pci_slot ();
@@ -68,7 +68,7 @@ int checkboard (void)
 void
 local_bus_init(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index d32274b2481..c6ad33018fb 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -82,7 +82,7 @@ struct cpld_data {
 
 int board_early_init_f(void)
 {
-	ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
+	ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR);
 	struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
 	/* Clock configuration to access CPLD using IFC(GPCM) */
 	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
@@ -131,7 +131,7 @@ int board_early_init_r(void)
 
 int config_board_mux(int ctrl_type)
 {
-	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u8 tmp;
 
 #if CONFIG_IS_ENABLED(DM_I2C)
@@ -625,21 +625,21 @@ void board_reset(void)
 
 int misc_init_r(void)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
-		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
-				MPC85xx_PMUXCR_CAN1_UART |
-				MPC85xx_PMUXCR_CAN2_TDM |
-				MPC85xx_PMUXCR_CAN2_UART);
+		clrbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_CAN1_TDM |
+				MPC85XX_PMUXCR_CAN1_UART |
+				MPC85XX_PMUXCR_CAN2_TDM |
+				MPC85XX_PMUXCR_CAN2_UART);
 		config_board_mux(MUX_TYPE_CAN);
 	} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
-		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
-				MPC85xx_PMUXCR_CAN1_UART);
-		setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
-				MPC85xx_PMUXCR_CAN1_TDM);
-		clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
-		setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
+		clrbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_CAN2_UART |
+				MPC85XX_PMUXCR_CAN1_UART);
+		setbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_CAN2_TDM |
+				MPC85XX_PMUXCR_CAN1_TDM);
+		clrbits_be32(&gur->pmuxcr2, MPC85XX_PMUXCR2_UART_GPIO);
+		setbits_be32(&gur->pmuxcr2, MPC85XX_PMUXCR2_UART_TDM);
 		config_board_mux(MUX_TYPE_TDM);
 	} else {
 		/* defaultly spi_cs_sel to flash */
@@ -652,7 +652,7 @@ int misc_init_r(void)
 		config_board_mux(MUX_TYPE_IFC);
 
 #ifdef CONFIG_TARGET_P1010RDB_PB
-	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
+	setbits_be32(&gur->pmuxcr2, MPC85XX_PMUXCR2_GPIO01_DRVVBUS);
 #endif
 	return 0;
 }
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index e450f626e0a..461ba372417 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c
@@ -28,7 +28,7 @@ phys_size_t get_effective_memsize(void)
 void board_init_f(ulong bootflag)
 {
 	u32 plat_ratio;
-	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
 	struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
 
 	console_init_f();
@@ -37,11 +37,11 @@ void board_init_f(ulong bootflag)
 	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
 
 #ifdef CONFIG_TARGET_P1010RDB_PB
-	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
+	setbits_be32(&gur->pmuxcr2, MPC85XX_PMUXCR2_GPIO01_DRVVBUS);
 #endif
 
 	/* initialize selected port with appropriate baud rate */
-	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85XX_PORPLLSR_PLAT_RATIO;
 	plat_ratio >>= 1;
 	gd->bus_clk = get_board_sys_clk() * plat_ratio;
 
diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c
index 8f0dec4c0ab..54cd7b9aacd 100644
--- a/board/freescale/p1010rdb/spl_minimal.c
+++ b/board/freescale/p1010rdb/spl_minimal.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
 void board_init_f(ulong bootflag)
 {
 	u32 plat_ratio;
-	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
 
 #if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM)
 	set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
@@ -28,7 +28,7 @@ void board_init_f(ulong bootflag)
 #endif
 
 	/* initialize selected port with appropriate baud rate */
-	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85XX_PORPLLSR_PLAT_RATIO;
 	plat_ratio >>= 1;
 	gd->bus_clk = get_board_sys_clk() * plat_ratio;
 
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 602b7f0156b..c3bd2837aa2 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -149,7 +149,7 @@ void board_cpld_init(void)
 void board_gpio_init(void)
 {
 #ifdef CONFIG_QE
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
 
 	/* Enable VSC7385 switch */
@@ -159,7 +159,7 @@ void board_gpio_init(void)
 	setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
 #else
 
-	ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
+	ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR);
 
 	/*
 	 * GPIO10 DDR Reset, open drain
@@ -197,17 +197,17 @@ void board_gpio_init(void)
 
 int board_early_init_f(void)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
-	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_CD);
+	setbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_SDHC_CD);
 #ifndef SDHC_WP_IS_GPIO
-	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_WP);
+	setbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_SDHC_WP);
 #endif
 	clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
 
-	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+	clrbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_SD_DATA);
 #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
-	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
+	setbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_TDM_ENA);
 #endif
 
 	board_gpio_init();
@@ -227,7 +227,7 @@ int board_early_init_f(void)
 int checkboard(void)
 {
 	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u8 in, out, invert, io_config, val;
 	int bus_num = CONFIG_SYS_SPD_BUS_NUM;
 
@@ -306,7 +306,7 @@ int checkboard(void)
 	puts("\n");
 
 	if (val & 0x1) {
-		setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+		setbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_SD_DATA);
 		puts("SD/MMC : 8-bit Mode\n");
 		puts("eSPI : Disabled\n");
 	} else {
@@ -368,7 +368,7 @@ int board_early_init_r(void)
 static void fix_max6370_watchdog(void *blob)
 {
 	int off = fdt_node_offset_by_compatible(blob, -1, "maxim,max6370");
-	ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
+	ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR);
 	u32 gpioval = in_be32(&pgpio->gpdat);
 
 	/*
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index 6c3f82849e3..e107ddefb0f 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -29,7 +29,7 @@ phys_size_t get_effective_memsize(void)
 void board_init_f(ulong bootflag)
 {
 	u32 plat_ratio, bus_clk;
-	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
 
 	/*
 	 * Call board_early_init_f() as early as possible as it workarounds
@@ -42,17 +42,17 @@ void board_init_f(ulong bootflag)
 	/* Set pmuxcr to allow both i2c1 and i2c2 */
 	setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
 	setbits_be32(&gur->pmuxcr,
-		     in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+		     in_be32(&gur->pmuxcr) | MPC85XX_PMUXCR_SD_DATA);
 
 	/* Read back the register to synchronize the write. */
 	in_be32(&gur->pmuxcr);
 
 #ifdef CONFIG_SPL_SPI_BOOT
-	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+	clrbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_SD_DATA);
 #endif
 
 	/* initialize selected port with appropriate baud rate */
-	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85XX_PORPLLSR_PLAT_RATIO;
 	plat_ratio >>= 1;
 	bus_clk = get_board_sys_clk() * plat_ratio;
 	gd->bus_clk = bus_clk;
diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
index f9e0b5b25ab..7bc7393894c 100644
--- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c
+++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
@@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
 void board_init_f(ulong bootflag)
 {
 	u32 plat_ratio;
-	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
 
 #if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM)
 	set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
@@ -27,7 +27,7 @@ void board_init_f(ulong bootflag)
 #endif
 
 	/* initialize selected port with appropriate baud rate */
-	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85XX_PORPLLSR_PLAT_RATIO;
 	plat_ratio >>= 1;
 	gd->bus_clk = get_board_sys_clk() * plat_ratio;
 
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 575259b19c0..b94aaa29f82 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -66,7 +66,7 @@ int checkboard(void)
 
 int board_early_init_f(void)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	/* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
 	setbits_be32(&gur->ddrclkdr, 0x000f000f);
@@ -81,7 +81,7 @@ int board_early_init_f(void)
 
 void board_config_lanes_mux(void)
 {
-	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
 	int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
 				FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
 
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index ad78f72f98c..8ccae53c77d 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -33,7 +33,7 @@ int board_eth_init(struct bd_info *bis)
 	struct memac_mdio_info dtsec_mdio_info;
 	struct memac_mdio_info tgec_mdio_info;
 	struct mii_dev *dev;
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 srds_s1;
 
 	srds_s1 = in_be32(&gur->rcwsr[4]) &
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index 9faf259af74..8a7c2309a15 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -29,7 +29,7 @@ phys_size_t get_effective_memsize(void)
 #define GPIO1_SD_SEL 0x00020000
 int board_mmc_getcd(struct mmc *mmc)
 {
-	ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
+	ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR);
 	u32 val = in_be32(&pgpio->gpdat);
 
 	/* GPIO1_14, 0: eMMC, 1: SD */
@@ -40,7 +40,7 @@ int board_mmc_getcd(struct mmc *mmc)
 
 int board_mmc_getwp(struct mmc *mmc)
 {
-	ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
+	ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR);
 	u32 val = in_be32(&pgpio->gpdat);
 
 	val &= GPIO1_SD_SEL;
@@ -52,7 +52,7 @@ int board_mmc_getwp(struct mmc *mmc)
 void board_init_f(ulong bootflag)
 {
 	u32 plat_ratio, sys_clk, ccb_clk;
-	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
 
 	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
 	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index baa59615b3e..2303aa8fb93 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -49,7 +49,7 @@ int checkboard(void)
 {
 	struct cpu_type *cpu = gd->arch.cpu;
 	static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
-	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 srds_s1;
 
 	srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@@ -99,7 +99,7 @@ int checkboard(void)
 #ifdef CONFIG_TARGET_T1024RDB
 static void board_mux_lane(void)
 {
-	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 srds_prtcl_s1;
 	u8 reg = CPLD_READ(misc_ctl_status);
 
@@ -222,7 +222,7 @@ static void fdt_enable_nor(void *blob)
 
 int board_mmc_getcd(struct mmc *mmc)
 {
-	ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
+	ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR);
 	u32 val = in_be32(&pgpio->gpdat);
 
 	/* GPIO1_14, 0: eMMC, 1: SD/MMC */
@@ -233,7 +233,7 @@ int board_mmc_getcd(struct mmc *mmc)
 
 int board_mmc_getwp(struct mmc *mmc)
 {
-	ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
+	ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR);
 	u32 val = in_be32(&pgpio->gpdat);
 
 	val &= GPIO1_SD_SEL;
@@ -243,8 +243,8 @@ int board_mmc_getwp(struct mmc *mmc)
 
 static u32 t1023rdb_ctrl(u32 ctrl_type)
 {
-	ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
-	ccsr_gur_t __iomem  *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR);
+	ccsr_gur_t __iomem  *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 val;
 	u8 tmp;
 	int bus_num = I2C_PCA6408_BUS_NUM;
@@ -274,7 +274,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type)
 		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
 		break;
 	case GPIO3_GET_VERSION:
-		pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR
+		pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85XX_GPIO_ADDR
 			 + GPIO3_OFFSET);
 		val = in_be32(&pgpio->gpdat);
 		val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
@@ -323,7 +323,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type)
 		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
 		break;
 	case GPIO3_GET_VERSION:
-		pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR
+		pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85XX_GPIO_ADDR
 			 + GPIO3_OFFSET);
 		val = in_be32(&pgpio->gpdat);
 		val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index dd8283f3c60..621cd781114 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -33,7 +33,7 @@ void board_init_f(ulong bootflag)
 	u32 porsr1, pinctl;
 	u32 svr = get_svr();
 #endif
-	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
 
 #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
 	if (IS_SVR_REV(svr, 1, 0)) {
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index 8cec71217a7..abc8224e4ef 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -93,7 +93,7 @@ int board_early_init_r(void)
 
 int misc_init_r(void)
 {
-	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 srds_s1;
 
 	srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index 569b193eab7..e1e21b950fe 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -189,7 +189,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 	const char *phyconn;
 	int off;
 
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 #ifdef CONFIG_TARGET_T2080QDS
 	serdes_corenet_t *srds_regs =
 		(void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
@@ -413,7 +413,7 @@ void fdt_fixup_board_enet(void *fdt)
  */
 static void initialize_lane_to_slot(void)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
 				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 
@@ -459,7 +459,7 @@ int board_eth_init(struct bd_info *bis)
 	int i, idx, lane, slot, interface;
 	struct memac_mdio_info dtsec_mdio_info;
 	struct memac_mdio_info tgec_mdio_info;
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
 	u32 srds_s1;
 
diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
index 8866be54a66..0dcb1411e58 100644
--- a/board/freescale/t208xqds/spl.c
+++ b/board/freescale/t208xqds/spl.c
@@ -67,7 +67,7 @@ unsigned long get_board_ddr_clk(void)
 void board_init_f(ulong bootflag)
 {
 	u32 plat_ratio, sys_clk, ccb_clk;
-	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
 
 	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
 	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
index 8be55e52e5f..cf70dda0e0a 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -88,7 +88,7 @@ int i2c_multiplexer_select_vid_channel(u8 channel)
 
 int brd_mux_lane_to_slot(void)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 srds_prtcl_s1;
 
 	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
index 130cb8847c0..e6794aa06de 100644
--- a/board/freescale/t208xrdb/spl.c
+++ b/board/freescale/t208xrdb/spl.c
@@ -27,7 +27,7 @@ phys_size_t get_effective_memsize(void)
 void board_init_f(ulong bootflag)
 {
 	u32 plat_ratio, sys_clk, ccb_clk;
-	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
 
 	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
 	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index 2e52543847b..43011f1edc2 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -43,7 +43,7 @@ int board_eth_init(struct bd_info *bis)
 	struct memac_mdio_info dtsec_mdio_info;
 	struct memac_mdio_info tgec_mdio_info;
 	struct mii_dev *dev;
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 srds_prtcl_s1, srds_prtcl_s2;
 
 	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
index 779457d2964..b705b20809b 100644
--- a/board/freescale/t4rdb/spl.c
+++ b/board/freescale/t4rdb/spl.c
@@ -33,7 +33,7 @@ phys_size_t get_effective_memsize(void)
 void board_init_f(ulong bootflag)
 {
 	u32 plat_ratio, sys_clk, ccb_clk;
-	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
 
 	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
 	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig
index a24d17cf8bf..7c80f1a0933 100644
--- a/board/keymile/Kconfig
+++ b/board/keymile/Kconfig
@@ -35,7 +35,7 @@ config KM_PHRAM
 config KM_RESERVED_PRAM
 	hex "Reserved RAM"
 	default 0x0 if MPC83XX
-	default 0x1000 if MPC85xx || ARCH_LS1021A
+	default 0x1000 if MPC85XX || ARCH_LS1021A
 	depends on !ARCH_SOCFPGA
 	help
 	  Reserved physical RAM area at the end of memory for special purposes.
@@ -79,7 +79,7 @@ config SYS_CLIPS_BASE
 config KM_COMMON_ETH_INIT
 	bool "Common Ethernet Initialization"
 	default y if MPC83XX
-	default n if MPC85xx || ARCH_SOCFPGA || ARCH_LS1021A
+	default n if MPC85XX || ARCH_SOCFPGA || ARCH_LS1021A
 	help
 	  Use the Ethernet initialization implemented in common code that
 	  detects if a Piggy board is present.
diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c
index ed552c57b5f..b75da715317 100644
--- a/board/keymile/kmcent2/kmcent2.c
+++ b/board/keymile/kmcent2/kmcent2.c
@@ -45,7 +45,7 @@ int checkboard(void)
 int board_early_init_f(void)
 {
 	struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	bool cpuwd_flag = false;
 
 	/* board specific IFC configuration: increased bus turnaround time */
@@ -221,8 +221,8 @@ EVENT_SPY(EVT_MISC_INIT_F, kmcent2_misc_init_f);
 int misc_init_r(void)
 {
 	serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
-	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_MPC85xx_SCFG;
-	ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CFG_SYS_MPC85xx_GUTS_ADDR;
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_MPC85XX_SCFG;
+	ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CFG_SYS_MPC85XX_GUTS_ADDR;
 
 	/* check SERDES bank 0 reference clock */
 	u32 actual = in_be32(&regs->bank[USED_SRDS_BANK].pllcr0);
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 9c4dd186fca..107d3c53eba 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -35,7 +35,7 @@ ulong flash_get_size (ulong base, int banknum);
 
 int checkboard (void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	char buf[64];
 	int f;
 	int i = env_get_f("serial#", buf, sizeof(buf));
@@ -139,7 +139,7 @@ int misc_init_r (void)
 void local_bus_init (void)
 {
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85XX_ECM_ADDR);
 	sys_info_t sysinfo;
 	uint clkdiv;
 	uint lbc_mhz;
@@ -175,7 +175,7 @@ void local_bus_init (void)
 #ifdef CONFIG_BOARD_EARLY_INIT_R
 int board_early_init_r (void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	/* set and reset the GPIO pin 2 which will reset the W83782G chip */
 	out_8((unsigned char*)&gur->gpoutdr, 0x3F );
diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile
index 002821916c4..6be05152aa4 100644
--- a/board/xes/common/Makefile
+++ b/board/xes/common/Makefile
@@ -5,6 +5,6 @@
 
 obj-$(CONFIG_MPC86xx)		+= fsl_8xxx_clk.o
 obj-$(CONFIG_ARCH_P2020)		+= fsl_8xxx_clk.o
-obj-$(CONFIG_MPC85xx)		+= fsl_8xxx_misc.o board.o
+obj-$(CONFIG_MPC85XX)		+= fsl_8xxx_misc.o board.o
 obj-$(CONFIG_MPC86xx)		+= fsl_8xxx_misc.o board.o
 obj-$(CONFIG_NAND_ACTL)	+= actl_nand.o
diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c
index c36b2afd50e..ef720c17240 100644
--- a/board/xes/common/fsl_8xxx_clk.c
+++ b/board/xes/common/fsl_8xxx_clk.c
@@ -12,8 +12,8 @@
  */
 unsigned long get_board_sys_clk(void)
 {
-#if defined(CONFIG_MPC85xx)
-	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+#if defined(CONFIG_MPC85XX)
+	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 #elif defined(CONFIG_MPC86xx)
 	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
@@ -29,14 +29,14 @@ unsigned long get_board_sys_clk(void)
 #endif
 }
 
-#ifdef CONFIG_MPC85xx
+#ifdef CONFIG_MPC85XX
 /*
  * Return DDR input clock - synchronous with SYSCLK or 66 MHz
  * Note: 86xx doesn't support asynchronous DDR clk
  */
 unsigned long get_board_ddr_clk(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
 
 	if (ddr_ratio == 0x7)
diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c
index bc7e5c5764f..3082acaaa04 100644
--- a/board/xes/common/fsl_8xxx_misc.c
+++ b/board/xes/common/fsl_8xxx_misc.c
@@ -27,8 +27,8 @@ int board_flash_wp_on(void)
  */
 uint get_board_derivative(void)
 {
-#if defined(CONFIG_MPC85xx)
-       volatile ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
+#if defined(CONFIG_MPC85XX)
+       volatile ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
 #elif defined(CONFIG_MPC86xx)
        volatile immap_t *immap = (immap_t *)CFG_SYS_CCSRBAR;
        volatile ccsr_gur_t *gur = &immap->im_gur;
diff --git a/boot/Kconfig b/boot/Kconfig
index fdcfbae7b2c..4bb1af23ac5 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -673,12 +673,12 @@ config SYS_MONITOR_BASE
 	  when booting from flash.
 
 config SPL_SYS_MONITOR_BASE
-	depends on MPC85xx && SPL && HAVE_SYS_MONITOR_BASE
+	depends on MPC85XX && SPL && HAVE_SYS_MONITOR_BASE
 	hex "Physical start address of SPL monitor code"
 	default SPL_TEXT_BASE
 
 config TPL_SYS_MONITOR_BASE
-	depends on MPC85xx && TPL && HAVE_SYS_MONITOR_BASE
+	depends on MPC85XX && TPL && HAVE_SYS_MONITOR_BASE
 	hex "Physical start address of TPL monitor code"
 
 config DYNAMIC_SYS_CLK_FREQ
diff --git a/common/Kconfig b/common/Kconfig
index e3a5e1be1e9..99ff67cac6a 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -709,7 +709,7 @@ config LAST_STAGE_INIT
 
 config MISC_INIT_R
 	bool "Execute Misc Init"
-	default y if ARCH_KEYSTONE || ARCH_SUNXI || MPC85xx
+	default y if ARCH_KEYSTONE || ARCH_SUNXI || MPC85XX
 	default y if ARCH_OMAP2PLUS && !AM33XX
 	help
 	  Enabling this option calls 'misc_init_r' function
diff --git a/common/board_r.c b/common/board_r.c
index 3618acad437..e4a5c88cdd4 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -130,7 +130,7 @@ static int initr_reloc_global_data(void)
 #elif !defined(CONFIG_SANDBOX) && !defined(CONFIG_NIOS2)
 	monitor_flash_len = (ulong)&__init_end - gd->relocaddr;
 #endif
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx)
 	/*
 	 * The gd->cpu pointer is set to an address in flash before relocation.
 	 * We need to update it to point to the same CPU entry in RAM.
diff --git a/common/memsize.c b/common/memsize.c
index 66d5be6a1ff..e8acc2be7a6 100644
--- a/common/memsize.c
+++ b/common/memsize.c
@@ -96,7 +96,7 @@ phys_size_t __weak get_effective_memsize(void)
 {
 	phys_size_t ram_size = gd->ram_size;
 
-#ifdef CONFIG_MPC85xx
+#ifdef CONFIG_MPC85XX
 	/*
 	 * Check for overflow and limit ram size to some representable value.
 	 * It is required that ram_base + ram_size must be representable by
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index 05034ce2e46..d93039d461a 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -6,7 +6,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b"
 CONFIG_ENV_ADDR=0xFFF60000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_SYS_SRIO=y
 CONFIG_SRIO1=y
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index 965c37e45ec..c34e3a26aba 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -6,7 +6,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
 CONFIG_ENV_ADDR=0xFFF60000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_SYS_SRIO=y
 CONFIG_SRIO1=y
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index 004175c8048..447624a464d 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -6,7 +6,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
 CONFIG_ENV_ADDR=0xFFF60000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_SYS_SRIO=y
 CONFIG_SRIO1=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index e0ffb164b5a..23a3650331e 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -13,7 +13,7 @@ CONFIG_TPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_P1010RDB_PA=y
 CONFIG_L2_CACHE=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index 71e17d90ec1..b52dd99c1e8 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
 CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_P1010RDB_PA=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index 0df2a559594..5152d3d8008 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -11,7 +11,7 @@ CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_P1010RDB_PA=y
 CONFIG_L2_CACHE=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index 086bfcb10e5..d2e3dc974b9 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -13,7 +13,7 @@ CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_P1010RDB_PA=y
 CONFIG_L2_CACHE=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index aa8aeda7580..1258d53aaa6 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -13,7 +13,7 @@ CONFIG_TPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_P1010RDB_PA=y
 CONFIG_L2_CACHE=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index 5807e8bdaa4..55f3b3e0232 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
 CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_P1010RDB_PA=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index 30ff3ad322b..41da013efd6 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -11,7 +11,7 @@ CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_P1010RDB_PA=y
 CONFIG_L2_CACHE=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index d7d8219e947..e33e7d5e711 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -13,7 +13,7 @@ CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_P1010RDB_PA=y
 CONFIG_L2_CACHE=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 6e053870834..1a81df7b3b2 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -13,7 +13,7 @@ CONFIG_TPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_P1010RDB_PB=y
 CONFIG_L2_CACHE=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index 7328c142f99..611052102f2 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
 CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_P1010RDB_PB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 216e14cdacc..7f6b79da634 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -11,7 +11,7 @@ CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_P1010RDB_PB=y
 CONFIG_L2_CACHE=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index 35943d10d77..40615cf9f88 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -13,7 +13,7 @@ CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_P1010RDB_PB=y
 CONFIG_L2_CACHE=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index c2c851ca57a..885db3d46a1 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -13,7 +13,7 @@ CONFIG_TPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_P1010RDB_PB=y
 CONFIG_L2_CACHE=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 0f109c514c1..12d92ef8807 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
 CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_P1010RDB_PB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index b8e0a92a935..e5d2caa0de0 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -11,7 +11,7 @@ CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_P1010RDB_PB=y
 CONFIG_L2_CACHE=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index f403e67b8fe..fc8ae9a3d6e 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -13,7 +13,7 @@ CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_P1010RDB_PB=y
 CONFIG_L2_CACHE=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 02f0f3cde99..c7a4ac8e519 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -12,7 +12,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 84cc6bd38e5..7ded32bcae1 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -10,7 +10,7 @@ CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index 427b67c6722..76e2e54853a 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -12,7 +12,7 @@ CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index e2373d04d74..fa13c807f88 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
 CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index e1e6af7fae0..57862fcea99 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -12,7 +12,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index d9477f1c339..bba95ed33df 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -10,7 +10,7 @@ CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index f27c9c3835d..419dd6f1b40 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -12,7 +12,7 @@ CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index ca828eac03d..9ca1294c6ff 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
 CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 1d364fef2aa..a6c5f96f13c 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -12,7 +12,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PD=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index 4dc2457c1c7..641793143d1 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -10,7 +10,7 @@ CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PD=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index bf6d2235b36..f023880f91c 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -12,7 +12,7 @@ CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PD=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index 5377aba4ef3..ec025fc332d 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
 CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PD=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 7646e9054b8..491f63e7bff 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -12,7 +12,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 81512593da5..464c35a7d5e 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -10,7 +10,7 @@ CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 3f106c60139..3b9e67e12ef 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -12,7 +12,7 @@ CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index d266ce82a59..ddb20ca5181 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
 CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 11d59d14fe4..44056761a65 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -12,7 +12,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index 9416d93c533..d85b38e3d67 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -10,7 +10,7 @@ CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 74d26f1f1a9..c5a226d06e5 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -12,7 +12,7 @@ CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index 4d5569c5549..d7f4449c556 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
 CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index bf3365a4800..39e909bf96f 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0xE0000
 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_SYS_SRIO=y
 CONFIG_SRIO1=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index 69f30d427f7..db53a06b965 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xCF400
 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_SYS_SRIO=y
 CONFIG_SRIO1=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index c2dc0f21eeb..ec0268dd745 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_SYS_SRIO=y
 CONFIG_SRIO1=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 306432e41b1..02cfe59feed 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_SYS_SRIO=y
 CONFIG_SRIO1=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index bedea018ddc..f8843df20c2 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -10,7 +10,7 @@ CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index f06bb02a27c..4674d2bd669 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -11,7 +11,7 @@ CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 4f91dce1094..24e6a6cb9e8 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -13,7 +13,7 @@ CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index c9d771e44bf..acee4e2aef8 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
 CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index a55797eb9e4..700614e3a20 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -9,7 +9,7 @@ CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index 2f5a1a329d0..288f41b0020 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -10,7 +10,7 @@ CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index afce81b1076..3c042483e59 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -12,7 +12,7 @@ CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 29b240fc147..ee87a349fe1 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -4,7 +4,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
 CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index ca960d368bd..a579998ef2a 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -9,7 +9,7 @@ CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_SYS_SRIO=y
 CONFIG_SRIO1=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index eba73ee989f..e214fe55215 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -10,7 +10,7 @@ CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_SYS_SRIO=y
 CONFIG_SRIO1=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index ae98a3586b7..dc4686c0818 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -2,7 +2,7 @@ CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_SYS_SRIO=y
 CONFIG_SRIO1=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 76a1e583007..1933f2a8ed4 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -12,7 +12,7 @@ CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_SYS_SRIO=y
 CONFIG_SRIO1=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index fe440a469f9..475cd65ca66 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -3,7 +3,7 @@ CONFIG_TEXT_BASE=0xFFF40000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_SYS_SRIO=y
 CONFIG_SRIO1=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index f4f90d5ab22..7c7f910eb2b 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -4,7 +4,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_SYS_SRIO=y
 CONFIG_SRIO1=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 18baf568121..d8475fd4051 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -9,7 +9,7 @@ CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index df98e33f971..e46e86a2389 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -10,7 +10,7 @@ CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index efa48af3bf8..e8a978656a6 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -12,7 +12,7 @@ CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 8e07b2a09c1..3051bbc3144 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -4,7 +4,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
 CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig
index 69bebfacb07..e228fcbda50 100644
--- a/configs/T2080RDB_revD_NAND_defconfig
+++ b/configs/T2080RDB_revD_NAND_defconfig
@@ -9,7 +9,7 @@ CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig
index 179fc63705a..4e56142e2ef 100644
--- a/configs/T2080RDB_revD_SDCARD_defconfig
+++ b/configs/T2080RDB_revD_SDCARD_defconfig
@@ -10,7 +10,7 @@ CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig
index 1d8a6b5f41c..99451afb592 100644
--- a/configs/T2080RDB_revD_SPIFLASH_defconfig
+++ b/configs/T2080RDB_revD_SPIFLASH_defconfig
@@ -12,7 +12,7 @@ CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig
index a1332a99b43..a0ee406f769 100644
--- a/configs/T2080RDB_revD_defconfig
+++ b/configs/T2080RDB_revD_defconfig
@@ -4,7 +4,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
 CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index d906035a2bf..f8122b04276 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -10,7 +10,7 @@ CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T4240RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index d2b270dd44f..62150389ba1 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -4,7 +4,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
 CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_T4240RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig
index d9aae79bc2b..aa18a419c8d 100644
--- a/configs/kmcent2_defconfig
+++ b/configs/kmcent2_defconfig
@@ -7,7 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="kmcent2"
 CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
 CONFIG_SYS_CLK_FREQ=66666666
 CONFIG_ENV_ADDR=0xebf20000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 CONFIG_TARGET_KMCENT2=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index a19d555f7d5..b853a6dbd2b 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -3,7 +3,7 @@ CONFIG_TEXT_BASE=0xf00000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="qemu-ppce500"
 CONFIG_SYS_CLK_FREQ=33000000
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_QEMU_PPCE500=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index 46be662037e..ba80ee1b16e 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="socrates"
 CONFIG_ENV_ADDR=0xFFF40000
 # CONFIG_SYS_PCI_64BIT is not set
-CONFIG_MPC85xx=y
+CONFIG_MPC85XX=y
 CONFIG_SYS_INIT_RAM_LOCK=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_SOCRATES=y
diff --git a/drivers/ata/fsl_sata.c b/drivers/ata/fsl_sata.c
index 972101b29ce..9aad2c6e2ad 100644
--- a/drivers/ata/fsl_sata.c
+++ b/drivers/ata/fsl_sata.c
@@ -78,7 +78,7 @@ static int init_sata(struct fsl_ata_priv *priv, int dev)
 		return -1;
 	}
 
-#ifdef CONFIG_MPC85xx
+#ifdef CONFIG_MPC85XX
 	if ((dev == 0) && (!is_serdes_configured(SATA1))) {
 		printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
 		return -1;
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index 5c928689a30..170f758ade6 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -166,7 +166,7 @@ endchoice
 endmenu
 
 config FSL_DMA
-	def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER
+	def_bool y if DDR_ECC && MPC85XX && !ECC_INIT_VIA_DDRCONTROLLER
 
 config DDR_ECC
 	bool "ECC DDR memory support"
@@ -199,7 +199,7 @@ config SYS_FSL_DDR_INTLV_256B
 endif
 
 menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
-	depends on MCF52x2 || MPC8xx || MPC83XX || MPC85xx
+	depends on MCF52x2 || MPC8xx || MPC83XX || MPC85XX
 
 config SYS_BR0_PRELIM_BOOL
 	bool "Define Bank 0"
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 8f8c2c864c3..e311d936383 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1854,7 +1854,7 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
 		/* clk_adjust in 5-bits on T-series and LS-series */
 		ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0x1F) << 22;
 	else
-		/* clk_adjust in 4-bits on earlier MPC85xx and P-series */
+		/* clk_adjust in 4-bits on earlier MPC85XX and P-series */
 		ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0xF) << 23;
 
 	debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
index b830e7cbd14..cadaaad01eb 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
@@ -20,8 +20,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	struct ccsr_ddr __iomem *ddr =
 		(struct ccsr_ddr __iomem *)CFG_SYS_FSL_DDR_ADDR;
 
-#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85XX)
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	uint svr;
 #endif
 
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 1c4a1cae4df..ff57423f57a 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -33,7 +33,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	int timeout;
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 	int timeout_save;
-	volatile ccsr_local_ecm_t *ecm = (void *)CFG_SYS_MPC85xx_ECM_ADDR;
+	volatile ccsr_local_ecm_t *ecm = (void *)CFG_SYS_MPC85XX_ECM_ADDR;
 	unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
 	int csn = -1;
 #endif
diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index 4f264c83f0c..938ed4429f7 100644
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -25,8 +25,8 @@
 
 #if defined(CONFIG_MPC83XX)
 dma83xx_t *dma_base = (void *)(CFG_SYS_MPC83XX_DMA_ADDR);
-#elif defined(CONFIG_MPC85xx)
-ccsr_dma_t *dma_base = (void *)(CFG_SYS_MPC85xx_DMA_ADDR);
+#elif defined(CONFIG_MPC85XX)
+ccsr_dma_t *dma_base = (void *)(CFG_SYS_MPC85XX_DMA_ADDR);
 #elif defined(CONFIG_MPC86xx)
 ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
 #else
@@ -35,7 +35,7 @@ ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
 
 static void dma_sync(void)
 {
-#if defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC85XX)
 	asm("sync; isync; msync");
 #elif defined(CONFIG_MPC86xx)
 	asm("sync; isync");
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 76e19918aad..70ed69b22e1 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -166,7 +166,7 @@ config SYS_I2C_FSL
        bool "Freescale I2C bus driver"
        help
 	  Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
-	  MPC85xx processors.
+	  MPC85XX processors.
 
 if SYS_I2C_FSL && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
 config SYS_FSL_I2C_OFFSET
diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c
index 1c5543e3c87..0b7d208d704 100644
--- a/drivers/net/fm/b4860.c
+++ b/drivers/net/fm/b4860.c
@@ -25,7 +25,7 @@ u32 port_to_devdisr[] = {
 
 static int is_device_disabled(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 devdisr2 = in_be32(&gur->devdisr2);
 
 	return port_to_devdisr[port] & devdisr2;
@@ -33,14 +33,14 @@ static int is_device_disabled(enum fm_port port)
 
 void fman_disable_port(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
 void fman_enable_port(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
@@ -51,7 +51,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
 	u32 serdes2_prtcl;
 	char buffer[HWCONFIG_BUFFER_SIZE];
 	char *buf = NULL;
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 #endif
 
 	if (is_device_disabled(port))
diff --git a/drivers/net/fm/p1023.c b/drivers/net/fm/p1023.c
index 9013b276bc9..a18e4e9b1f7 100644
--- a/drivers/net/fm/p1023.c
+++ b/drivers/net/fm/p1023.c
@@ -10,13 +10,13 @@
 #include <asm/fsl_serdes.h>
 
 static u32 port_to_devdisr[] = {
-	[FM1_DTSEC1] = MPC85xx_DEVDISR_TSEC1,
-	[FM1_DTSEC2] = MPC85xx_DEVDISR_TSEC2,
+	[FM1_DTSEC1] = MPC85XX_DEVDISR_TSEC1,
+	[FM1_DTSEC2] = MPC85XX_DEVDISR_TSEC2,
 };
 
 static int is_device_disabled(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 devdisr = in_be32(&gur->devdisr);
 
 	return port_to_devdisr[port] & devdisr;
@@ -24,7 +24,7 @@ static int is_device_disabled(enum fm_port port)
 
 void fman_disable_port(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	/* don't allow disabling of DTSEC1 as its needed for MDIO */
 	if (port == FM1_DTSEC1)
@@ -35,14 +35,14 @@ void fman_disable_port(enum fm_port port)
 
 void fman_enable_port(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	clrbits_be32(&gur->devdisr, port_to_devdisr[port]);
 }
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 pordevsr = in_be32(&gur->pordevsr);
 
 	if (is_device_disabled(port))
@@ -52,8 +52,8 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
 	if (port == FM1_DTSEC1) {
 		if (is_serdes_configured(SGMII_FM1_DTSEC1))
 			return PHY_INTERFACE_MODE_SGMII;
-		if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS) {
-			if (pordevsr & MPC85xx_PORDEVSR_TSEC1_PRTC)
+		if (pordevsr & MPC85XX_PORDEVSR_SGMII1_DIS) {
+			if (pordevsr & MPC85XX_PORDEVSR_TSEC1_PRTC)
 				return PHY_INTERFACE_MODE_RGMII;
 			else
 				return PHY_INTERFACE_MODE_RMII;
@@ -64,7 +64,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
 	if (port == FM1_DTSEC2) {
 		if (is_serdes_configured(SGMII_FM1_DTSEC2))
 			return PHY_INTERFACE_MODE_SGMII;
-		if (pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)
+		if (pordevsr & MPC85XX_PORDEVSR_SGMII2_DIS)
 			return PHY_INTERFACE_MODE_RGMII;
 	}
 
diff --git a/drivers/net/fm/p4080.c b/drivers/net/fm/p4080.c
index 7ad993221f7..3e4c2234357 100644
--- a/drivers/net/fm/p4080.c
+++ b/drivers/net/fm/p4080.c
@@ -24,7 +24,7 @@ static u32 port_to_devdisr[] = {
 
 static int is_device_disabled(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 devdisr2 = in_be32(&gur->devdisr2);
 
 	return port_to_devdisr[port] & devdisr2;
@@ -32,7 +32,7 @@ static int is_device_disabled(enum fm_port port)
 
 void fman_disable_port(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	/* don't allow disabling of DTSEC1 as its needed for MDIO */
 	if (port == FM1_DTSEC1)
@@ -43,14 +43,14 @@ void fman_disable_port(enum fm_port port)
 
 void fman_enable_port(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
 
 	if (is_device_disabled(port))
diff --git a/drivers/net/fm/p5020.c b/drivers/net/fm/p5020.c
index f931491b112..86f8a55179b 100644
--- a/drivers/net/fm/p5020.c
+++ b/drivers/net/fm/p5020.c
@@ -20,7 +20,7 @@ static u32 port_to_devdisr[] = {
 
 static int is_device_disabled(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 devdisr2 = in_be32(&gur->devdisr2);
 
 	return port_to_devdisr[port] & devdisr2;
@@ -28,7 +28,7 @@ static int is_device_disabled(enum fm_port port)
 
 void fman_disable_port(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	/* don't allow disabling of DTSEC1 as its needed for MDIO */
 	if (port == FM1_DTSEC1)
@@ -39,14 +39,14 @@ void fman_disable_port(enum fm_port port)
 
 void fman_enable_port(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
 
 	if (is_device_disabled(port))
diff --git a/drivers/net/fm/p5040.c b/drivers/net/fm/p5040.c
index ef9f4bcce4d..ca3e260082d 100644
--- a/drivers/net/fm/p5040.c
+++ b/drivers/net/fm/p5040.c
@@ -26,7 +26,7 @@ u32 port_to_devdisr[] = {
 
 static int is_device_disabled(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 devdisr2 = in_be32(&gur->devdisr2);
 
 	return port_to_devdisr[port] & devdisr2;
@@ -34,7 +34,7 @@ static int is_device_disabled(enum fm_port port)
 
 void fman_disable_port(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	/* don't allow disabling of DTSEC1 as its needed for MDIO */
 	if (port == FM1_DTSEC1)
@@ -45,14 +45,14 @@ void fman_disable_port(enum fm_port port)
 
 void fman_enable_port(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
 
 	if (is_device_disabled(port))
diff --git a/drivers/net/fm/t1024.c b/drivers/net/fm/t1024.c
index 70ab4610cdf..6e20c5d923d 100644
--- a/drivers/net/fm/t1024.c
+++ b/drivers/net/fm/t1024.c
@@ -20,7 +20,7 @@ u32 port_to_devdisr[] = {
 
 static int is_device_disabled(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 devdisr2 = in_be32(&gur->devdisr2);
 
 	return port_to_devdisr[port] & devdisr2;
@@ -28,14 +28,14 @@ static int is_device_disabled(enum fm_port port)
 
 void fman_disable_port(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
 
 	if (is_device_disabled(port))
diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c
index 5c260bed7fd..1541d8a6a33 100644
--- a/drivers/net/fm/t1040.c
+++ b/drivers/net/fm/t1040.c
@@ -11,7 +11,7 @@
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
 
 	/* handle RGMII first */
diff --git a/drivers/net/fm/t2080.c b/drivers/net/fm/t2080.c
index 6174934d2b8..d1fec51baed 100644
--- a/drivers/net/fm/t2080.c
+++ b/drivers/net/fm/t2080.c
@@ -28,7 +28,7 @@ u32 port_to_devdisr[] = {
 
 static int is_device_disabled(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 devdisr2 = in_be32(&gur->devdisr2);
 
 	return port_to_devdisr[port] & devdisr2;
@@ -36,14 +36,14 @@ static int is_device_disabled(enum fm_port port)
 
 void fman_disable_port(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
 
 	if (is_device_disabled(port))
diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c
index f0a02bfe457..3d129d88362 100644
--- a/drivers/net/fm/t4240.c
+++ b/drivers/net/fm/t4240.c
@@ -35,7 +35,7 @@ u32 port_to_devdisr[] = {
 
 static int is_device_disabled(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 devdisr2 = in_be32(&gur->devdisr2);
 
 	return port_to_devdisr[port] & devdisr2;
@@ -43,21 +43,21 @@ static int is_device_disabled(enum fm_port port)
 
 void fman_disable_port(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
 void fman_enable_port(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 
 	clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
 
 	if (is_device_disabled(port))
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ef328d26525..5ad5fe916d2 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -150,14 +150,14 @@ config PCIE_FSL
 	select SYS_FSL_PCI_VER_3_X if ARCH_T2080 || ARCH_T4240
 	help
 	  Say Y here if you want to enable PCIe controller support on FSL
-	  PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs.
+	  PowerPC MPC85XX, MPC86xx, B series, P series and T series SoCs.
 	  This driver does not support SRIO_PCIE_BOOT feature.
 
 config PCI_MPC85XX
 	bool "MPC85XX PowerPC PCI support"
 	help
 	  Say Y here if you want to enable PCI controller support on FSL
-	  PowerPC MPC85xx SoC.
+	  PowerPC MPC85XX SoC.
 
 config PCI_MSC01
 	bool "MSC01 PCI support"
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 2825dc6f9aa..2ea6b56516e 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -25,7 +25,7 @@
 #include <asm/arch/cpu.h>
 #endif
 
-#define MPC85xx_DEVDISR_QE_DISABLE	0x1
+#define MPC85XX_DEVDISR_QE_DISABLE	0x1
 
 qe_map_t		*qe_immr;
 #ifdef CONFIG_QE
@@ -469,7 +469,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
 #ifdef CONFIG_ARCH_LS1021A
 	struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
 #else
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 #endif
 #endif
 	if (!firmware) {
@@ -485,7 +485,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
 	    (hdr->magic[2] != 'F')) {
 		printf("QE microcode not found\n");
 #ifdef CONFIG_DEEP_SLEEP
-		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
+		setbits_be32(&gur->devdisr, MPC85XX_DEVDISR_QE_DISABLE);
 #endif
 		return -EPERM;
 	}
@@ -609,7 +609,7 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware)
 #ifdef CONFIG_ARCH_LS1021A
 	struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
 #else
-	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 #endif
 #endif
 	if (!firmware) {
@@ -625,7 +625,7 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware)
 	    (hdr->magic[2] != 'F')) {
 		printf("Not a microcode\n");
 #ifdef CONFIG_DEEP_SLEEP
-		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
+		setbits_be32(&gur->devdisr, MPC85XX_DEVDISR_QE_DISABLE);
 #endif
 		return -EPERM;
 	}
@@ -718,7 +718,7 @@ int u_qe_firmware_resume(const struct qe_firmware *firmware, qe_map_t *qe_immrr)
 	const u32 *code;
 #ifdef CONFIG_DEEP_SLEEP
 #ifdef CONFIG_PPC
-	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
 #else
 	struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
 #endif
@@ -733,7 +733,7 @@ int u_qe_firmware_resume(const struct qe_firmware *firmware, qe_map_t *qe_immrr)
 	if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
 	    (hdr->magic[2] != 'F')) {
 #ifdef CONFIG_DEEP_SLEEP
-		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
+		setbits_be32(&gur->devdisr, MPC85XX_DEVDISR_QE_DISABLE);
 #endif
 		return -EPERM;
 	}
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index b1d964d79d0..5ce9d73570b 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -390,7 +390,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	if (!fsl)
 		return NULL;
 
-	fsl->espi = (void *)(CFG_SYS_MPC85xx_ESPI_ADDR);
+	fsl->espi = (void *)(CFG_SYS_MPC85XX_ESPI_ADDR);
 	fsl->mode = mode;
 	fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
 	fsl->speed_hz = max_hz;
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 6213b3c95fa..930e6885cbb 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -291,7 +291,7 @@ config EHCI_HCD_INIT_AFTER_RESET
 config USB_EHCI_FSL
 	bool  "Support for FSL on-chip EHCI USB controller"
 	select EHCI_HCD_INIT_AFTER_RESET
-	select SYS_FSL_USB_INTERNAL_UTMI_PHY if MPC85xx && \
+	select SYS_FSL_USB_INTERNAL_UTMI_PHY if MPC85XX && \
 		!(ARCH_B4860 || ARCH_B4420 || ARCH_P4080 || ARCH_P1020 || ARCH_P2020)
 	---help---
 	  Enables support for the on-chip EHCI controller on FSL chips.
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index b5ac8f7f50d..9218de06e22 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -140,10 +140,10 @@ config WDT_BCM6345
 
 config WDT_BOOKE
 	bool "PowerPC Book-E watchdog driver"
-	depends on WDT && MPC85xx
+	depends on WDT && MPC85XX
 	help
 	  Watchdog driver for PowerPC Book-E chips, such as the Freescale
-	  MPC85xx SOCs and the IBM PowerPC 440.
+	  MPC85XX SOCs and the IBM PowerPC 440.
 
 config WDT_CDNS
 	bool "Cadence watchdog timer support"
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 9efae58ce90..eec51744696 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -340,7 +340,7 @@ extern unsigned long get_sdram_size(void);
 #endif
 
 #ifdef CONFIG_MMC
-#define CFG_SYS_FSL_ESDHC_ADDR	CFG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR	CFG_SYS_MPC85XX_ESDHC_ADDR
 #endif
 
 /*
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 28f53ae78a1..4f74a1695e0 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -284,7 +284,7 @@
 #endif
 
 #ifdef CONFIG_MMC
-#define CFG_SYS_FSL_ESDHC_ADDR       CFG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR       CFG_SYS_MPC85XX_ESDHC_ADDR
 #endif
 
 /*
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 7ee46abffdb..22b1e750825 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -347,7 +347,7 @@
  * SDHC
  */
 #ifdef CONFIG_MMC
-#define CFG_SYS_FSL_ESDHC_ADDR	CFG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR	CFG_SYS_MPC85XX_ESDHC_ADDR
 #endif
 
 /* Qman/Bman */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index f196bd76e6e..e0d0436c197 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -304,7 +304,7 @@
 */
 
 #ifdef CONFIG_MMC
-#define CFG_SYS_FSL_ESDHC_ADDR       CFG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR       CFG_SYS_MPC85XX_ESDHC_ADDR
 #endif
 
 /* Qman/Bman */
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 2023d7497f6..43fcf6ff13e 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -389,7 +389,7 @@
  * SDHC
  */
 #ifdef CONFIG_MMC
-#define CFG_SYS_FSL_ESDHC_ADDR	CFG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR	CFG_SYS_MPC85XX_ESDHC_ADDR
 #endif
 
 /*
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index f213d2de770..21f06e97a44 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -351,7 +351,7 @@
  * SDHC
  */
 #ifdef CONFIG_MMC
-#define CFG_SYS_FSL_ESDHC_ADDR	CFG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR	CFG_SYS_MPC85XX_ESDHC_ADDR
 #endif
 
 /*
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 506f1b7e268..e6daf0ef00c 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -350,7 +350,7 @@
 */
 
 #ifdef CONFIG_MMC
-#define CFG_SYS_FSL_ESDHC_ADDR       CFG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR       CFG_SYS_MPC85XX_ESDHC_ADDR
 #endif
 
 
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index f5bd0913449..7fd68c70fc6 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -373,7 +373,7 @@
  */
 
 #ifdef CONFIG_MMC
-#define CFG_SYS_FSL_ESDHC_ADDR	CFG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR	CFG_SYS_MPC85XX_ESDHC_ADDR
 #endif
 
 /*
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 2b35be83ec6..5e7317d30a3 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -21,7 +21,7 @@
  */
 
 /*
- * sysclk for MPC85xx
+ * sysclk for MPC85XX
  *
  * Two valid values are:
  *    33000000
diff --git a/include/e500.h b/include/e500.h
index 9f68a834c2f..6343393e5f5 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -38,7 +38,7 @@ typedef struct
 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 	unsigned char diff_sysclk;
 #endif
-} MPC85xx_SYS_INFO;
+} MPC85XX_SYS_INFO;
 
 #endif  /* _ASMLANGUAGE */
 
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index c43f780e4cd..042faa8b2c3 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -465,7 +465,7 @@ int fsl_dp_resume(void);
  * The 85xx boards have a common prototype for fixed_sdram so put the
  * declaration here.
  */
-#ifdef CONFIG_MPC85xx
+#ifdef CONFIG_MPC85XX
 extern phys_size_t fixed_sdram(void);
 #endif
 
diff --git a/include/fsl_fman.h b/include/fsl_fman.h
index 74acdb25691..f1857a7ef96 100644
--- a/include/fsl_fman.h
+++ b/include/fsl_fman.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * MPC85xx Internal Memory Map
+ * MPC85XX Internal Memory Map
  *
  * Copyright 2010-2011 Freescale Semiconductor, Inc.
  */
diff --git a/include/ioports.h b/include/ioports.h
index 1cd3ceb37a5..f253e002b0e 100644
--- a/include/ioports.h
+++ b/include/ioports.h
@@ -23,7 +23,7 @@ typedef struct {
  * the internal memory map aligns the above structure on
  * a 0x20 byte boundary
  */
-#ifdef CONFIG_MPC85xx
+#ifdef CONFIG_MPC85XX
 #define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20))
 #else
 #define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
diff --git a/include/mpc85xx.h b/include/mpc85xx.h
index 636734dd3c6..e26e131114c 100644
--- a/include/mpc85xx.h
+++ b/include/mpc85xx.h
@@ -3,8 +3,8 @@
  * Copyright(c) 2003 Motorola Inc.
  */
 
-#ifndef	__MPC85xx_H__
-#define __MPC85xx_H__
+#ifndef	__MPC85XX_H__
+#define __MPC85XX_H__
 
 #if defined(CONFIG_E500)
 #include <e500.h>
@@ -60,4 +60,4 @@ CFG_SYS_CCSRBAR_PHYS_LOW and/or CFG_SYS_CCSRBAR_PHYS_HIGH instead."
 #define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
 				 CFG_SYS_CCSRBAR_PHYS_LOW)
 
-#endif	/* __MPC85xx_H__ */
+#endif	/* __MPC85XX_H__ */
diff --git a/include/pci.h b/include/pci.h
index c55d6107a49..6e58cd9a10b 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -770,7 +770,7 @@ int pci_hose_find_ext_capability(struct pci_controller *hose,
 const char * pci_class_str(u8 class);
 int pci_last_busno(void);
 
-#ifdef CONFIG_MPC85xx
+#ifdef CONFIG_MPC85XX
 extern void pci_mpc85xx_init (struct pci_controller *hose);
 #endif
 
diff --git a/include/post.h b/include/post.h
index 41120695064..6c036e4fffc 100644
--- a/include/post.h
+++ b/include/post.h
@@ -25,9 +25,9 @@
 #include <linux/immap_qe.h>
 #define _POST_WORD_ADDR	(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
 
-#elif defined (CONFIG_MPC85xx)
+#elif defined (CONFIG_MPC85XX)
 #include <asm/immap_85xx.h>
-#define _POST_WORD_ADDR	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PIC_OFFSET + \
+#define _POST_WORD_ADDR	(CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_PIC_OFFSET + \
 				offsetof(ccsr_pic_t, tfrr))
 #endif
 
diff --git a/include/serial.h b/include/serial.h
index ceab714f541..22ac1043d36 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -27,7 +27,7 @@ extern struct serial_device serial_smh_device;
 extern struct serial_device serial_scc_device;
 extern struct serial_device *default_serial_console(void);
 
-#if	defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || \
+#if	defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85XX) || \
 	defined(CONFIG_MPC86xx) || \
 	defined(CONFIG_ARCH_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \
 	defined(CONFIG_MICROBLAZE)
diff --git a/include/watchdog.h b/include/watchdog.h
index ac5f11e376f..ddc81cd6c76 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -40,7 +40,7 @@ int init_func_watchdog_reset(void);
 	void hw_watchdog_init(void);
 #endif
 
-#if defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC85XX)
 	void init_85xx_watchdog(void);
 #endif
 #endif /* _WATCHDOG_H_ */
