@@ -31,7 +31,7 @@ int platform_sys_info(struct sys_info *si)
#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define bi_bar bi_immr_base
-#elif defined(CONFIG_MPC83xx)
+#elif defined(CONFIG_MPC83XX)
#define bi_bar bi_immrbar
#endif
@@ -370,7 +370,7 @@ config SYS_IMMR
depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
default 0xFF000000 if MPC8xx
default 0xF0000000 if ARCH_MPC8313
- default 0xE0000000 if MPC83xx && !ARCH_MPC8313
+ default 0xE0000000 if MPC83XX && !ARCH_MPC8313
default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
@@ -8,8 +8,8 @@ choice
prompt "CPU select"
optional
-config MPC83xx
- bool "MPC83xx"
+config MPC83XX
+ bool "MPC83XX"
select CREATE_ARCH_SYMLINK
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -36,7 +36,7 @@ endchoice
config FSL_LBC
def_bool y
- depends on (MPC85xx || MPC83xx) && !FSL_IFC
+ depends on (MPC85xx || MPC83XX) && !FSL_IFC
config HIGH_BATS
bool "Enable high BAT registers"
@@ -46,7 +46,7 @@ config HIGH_BATS
config SYS_INIT_RAM_LOCK
bool "Lock some portion of L1 for initial ram stack"
- depends on MPC83xx || MPC85xx
+ depends on MPC83XX || MPC85xx
config SYS_SRIO
bool "Serial RapidIO support"
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
-obj-$(CONFIG_MPC83xx) += mpc8xxx/
+obj-$(CONFIG_MPC83XX) += mpc8xxx/
obj-$(CONFIG_MPC85xx) += mpc8xxx/
obj-$(CONFIG_MPC86xx) += mpc8xxx/
@@ -1,5 +1,5 @@
menu "mpc83xx CPU"
- depends on MPC83xx
+ depends on MPC83XX
config DEFAULT_IMMR
hex
@@ -90,7 +90,7 @@ endchoice
config MPC83XX_QUICC_ENGINE
bool
-# TODO: Imply MPC83xx PCI driver
+# TODO: Imply MPC83XX PCI driver
config MPC83XX_PCI_SUPPORT
bool
@@ -4,7 +4,7 @@
*/
/*
- * CPU specific code for the MPC83xx family.
+ * CPU specific code for the MPC83XX family.
*
* Derived from the MPC8260 and MPC85xx.
*/
@@ -7,7 +7,7 @@
*/
/*
- * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
+ * U-Boot - Startup Code for MPC83XX PowerPC based Embedded Boards
*/
#include <asm-offsets.h>
@@ -8,7 +8,7 @@
#include <init.h>
#include <asm/fsl_lbc.h>
-#ifdef CONFIG_MPC83xx
+#ifdef CONFIG_MPC83XX
#include "../mpc83xx/elbc/elbc.h"
#endif
@@ -10,7 +10,7 @@
#include <asm/types.h>
-#ifdef CONFIG_MPC83xx
+#ifdef CONFIG_MPC83XX
typedef struct fsl_dma {
uint mr; /* DMA mode register */
#define FSL_DMA_MR_CS 0x00000001 /* Channel start */
@@ -111,7 +111,7 @@ typedef struct fsl_dma {
uint dsr; /* DMA destination stride register */
char res4[56];
} fsl_dma_t;
-#endif /* !CONFIG_MPC83xx */
+#endif /* !CONFIG_MPC83XX */
#ifdef CONFIG_FSL_DMA
void dma_init(void);
@@ -324,7 +324,7 @@ void lbc_sdram_init(void);
*/
#define LCRR_CLKDIV 0x0000001F
#define LCRR_CLKDIV_SHIFT 0
-#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
+#if defined(CONFIG_MPC83XX) || defined(CONFIG_ARCH_MPC8540) || \
defined(CONFIG_ARCH_MPC8560)
#define LCRR_CLKDIV_2 0x00000002
#define LCRR_CLKDIV_4 0x00000004
@@ -21,7 +21,7 @@ struct arch_global_data {
unsigned long brg_clk;
#endif
/* TODO: sjg@chromium.org: Should these be unslgned long? */
-#if defined(CONFIG_MPC83xx)
+#if defined(CONFIG_MPC83XX)
#ifdef CONFIG_CLK_MPC83XX
u32 core_clk;
#else
@@ -57,7 +57,7 @@ struct arch_global_data {
u32 lbc_clk;
void *cpu;
#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
-#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
+#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx)
u32 i2c1_clk;
u32 i2c2_clk;
@@ -75,7 +75,7 @@ struct arch_global_data {
u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
#endif
unsigned long reset_status; /* reset status register at boot */
-#if defined(CONFIG_MPC83xx)
+#if defined(CONFIG_MPC83XX)
unsigned long arbiter_event_attributes;
unsigned long arbiter_event_address;
#endif
@@ -2,7 +2,7 @@
/*
* Copyright 2004-2011 Freescale Semiconductor, Inc.
*
- * MPC83xx Internal Memory Map
+ * MPC83XX Internal Memory Map
*
* Contributors:
* Dave Liu <daveliu@freescale.com>
@@ -864,12 +864,12 @@ struct ccsr_gpio {
#define CFG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
#define CFG_SYS_FSL_DDR_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
-#define CFG_SYS_MPC83xx_DMA_OFFSET (0x8000)
-#define CFG_SYS_MPC83xx_DMA_ADDR \
- (CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_DMA_OFFSET)
-#define CFG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
-#define CFG_SYS_MPC83xx_ESDHC_ADDR \
- (CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET)
+#define CFG_SYS_MPC83XX_DMA_OFFSET (0x8000)
+#define CFG_SYS_MPC83XX_DMA_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC83XX_DMA_OFFSET)
+#define CFG_SYS_MPC83XX_ESDHC_OFFSET (0x2e000)
+#define CFG_SYS_MPC83XX_ESDHC_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC83XX_ESDHC_OFFSET)
#define CFG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
@@ -19,7 +19,7 @@
#include <mpc85xx.h>
#include <asm/immap_85xx.h>
#endif
-#ifdef CONFIG_MPC83xx
+#ifdef CONFIG_MPC83XX
#include <mpc83xx.h>
#include <asm/immap_83xx.h>
#endif
@@ -52,7 +52,7 @@ static inline uint get_svr(void)
#if defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || \
- defined(CONFIG_MPC83xx)
+ defined(CONFIG_MPC83XX)
unsigned char in8(unsigned int);
void out8(unsigned int, unsigned char);
unsigned short in16(unsigned int);
@@ -68,7 +68,7 @@ void ppcDcbi(unsigned long value);
void ppcSync(void);
void ppcDcbz(unsigned long value);
#endif
-#if defined(CONFIG_MPC83xx)
+#if defined(CONFIG_MPC83XX)
void ppcDWload(unsigned int *addr, unsigned int *ret);
void ppcDWstore(unsigned int *addr, unsigned int *value);
void disable_addr_trans(void);
@@ -1004,7 +1004,7 @@
#if defined(CONFIG_MPC85xx)
#define IS_E_PROCESSOR(svr) (svr & 0x80000)
#else
-#if defined(CONFIG_MPC83xx)
+#if defined(CONFIG_MPC83XX)
#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000))
#endif
#endif
@@ -1163,7 +1163,7 @@ int fsl_qoriq_dsp_core_to_cluster(unsigned int core);
#define CPU_TYPE_ENTRY_MASK(n, v, nc, m) \
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), .mask = (m) }
#else
-#if defined(CONFIG_MPC83xx)
+#if defined(CONFIG_MPC83XX)
#define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
#endif
#endif
@@ -20,7 +20,7 @@ int arch_setup_bdinfo(void)
bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
#endif
-#if defined(CONFIG_MPC83xx)
+#if defined(CONFIG_MPC83XX)
bd->bi_immrbar = CONFIG_SYS_IMMR;
#endif
@@ -52,7 +52,7 @@ Freescale MPC837xE-RDB Board
include/configs/MPC837XERDB.h
- CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360
+ CONFIG_MPC83XX MPC83XX family for both MPC8349 and MPC8360
CONFIG_MPC837x MPC837x specific
CONFIG_MPC837XERDB MPC837xE-RDB board specific
@@ -34,7 +34,7 @@ config KM_PHRAM
config KM_RESERVED_PRAM
hex "Reserved RAM"
- default 0x0 if MPC83xx
+ default 0x0 if MPC83XX
default 0x1000 if MPC85xx || ARCH_LS1021A
depends on !ARCH_SOCFPGA
help
@@ -78,7 +78,7 @@ config SYS_CLIPS_BASE
config KM_COMMON_ETH_INIT
bool "Common Ethernet Initialization"
- default y if MPC83xx
+ default y if MPC83XX
default n if MPC85xx || ARCH_SOCFPGA || ARCH_LS1021A
help
Use the Ethernet initialization implemented in common code that
@@ -1,5 +1,5 @@
menu "KM 83xx Options"
- depends on MPC83xx
+ depends on MPC83XX
config KM_ENABLE_FULL_DM_DTS_SUPPORT
bool "enable full DM/DTS support for KM 83xx boards"
@@ -7,7 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb"
CONFIG_SYS_CLK_FREQ=66666667
CONFIG_ENV_ADDR=0xFE080000
# CONFIG_SYS_PCI_64BIT is not set
-CONFIG_MPC83xx=y
+CONFIG_MPC83XX=y
CONFIG_HIGH_BATS=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_MPC837XERDB=y
@@ -9,7 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="gazerbeam"
CONFIG_IDENT_STRING=" gazerbeam 0.01"
CONFIG_SYS_CLK_FREQ=33333333
CONFIG_ENV_ADDR=0xFE080000
-CONFIG_MPC83xx=y
+CONFIG_MPC83XX=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_GAZERBEAM=y
CONFIG_SYSTEM_PLL_VCO_DIV_2=y
@@ -7,7 +7,7 @@ CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ENV_ADDR=0xF00C0000
-CONFIG_MPC83xx=y
+CONFIG_MPC83XX=y
CONFIG_HIGH_BATS=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_KMCOGE5NE=y
@@ -8,7 +8,7 @@ CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ENV_ADDR=0xF00C0000
-CONFIG_MPC83xx=y
+CONFIG_MPC83XX=y
CONFIG_HIGH_BATS=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_KMETER1=y
@@ -7,7 +7,7 @@ CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ENV_ADDR=0xF00C0000
-CONFIG_MPC83xx=y
+CONFIG_MPC83XX=y
CONFIG_HIGH_BATS=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_KMOPTI2=y
@@ -7,7 +7,7 @@ CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ENV_ADDR=0xF00C0000
-CONFIG_MPC83xx=y
+CONFIG_MPC83XX=y
CONFIG_HIGH_BATS=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_KMSUPX5=y
@@ -7,7 +7,7 @@ CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ENV_ADDR=0xF00C0000
-CONFIG_MPC83xx=y
+CONFIG_MPC83XX=y
CONFIG_HIGH_BATS=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_KMTEPR2=y
@@ -7,7 +7,7 @@ CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ENV_ADDR=0xF00C0000
-CONFIG_MPC83xx=y
+CONFIG_MPC83XX=y
CONFIG_HIGH_BATS=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_TUGE1=y
@@ -7,7 +7,7 @@ CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ENV_ADDR=0xF00C0000
-CONFIG_MPC83xx=y
+CONFIG_MPC83XX=y
CONFIG_HIGH_BATS=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_TUXX1=y
@@ -138,10 +138,10 @@ config CLK_K210_SET_RATE
feature adds around 1K to U-Boot's final size.
config CLK_MPC83XX
- bool "Enable MPC83xx clock driver"
+ bool "Enable MPC83XX clock driver"
depends on CLK
help
- Support for the clock driver of the MPC83xx series of SoCs.
+ Support for the clock driver of the MPC83XX series of SoCs.
config CLK_OCTEON
bool "Clock controller driver for Marvell MIPS Octeon"
@@ -22,7 +22,7 @@
DECLARE_GLOBAL_DATA_PTR;
/**
- * struct mpc83xx_clk_priv - Private data structure for the MPC83xx clock
+ * struct mpc83xx_clk_priv - Private data structure for the MPC83XX clock
* driver
* @speed: Array containing the speed values of all system clocks (initialized
* once, then only read back)
@@ -286,7 +286,7 @@ static ulong mpc83xx_clk_get_rate(struct clk *clk)
static int mpc83xx_clk_enable(struct clk *clk)
{
- /* MPC83xx clocks are always enabled */
+ /* MPC83XX clocks are always enabled */
return 0;
}
@@ -172,12 +172,12 @@ static void set_mode(struct clk_mode *mode, u8 low, u8 high, int type)
* retrieve_mode() - Get the clock mode description for a specific clock
* @clk: The identifier of the clock for which the clock description should
* be retrieved
- * @soc_type: The type of MPC83xx SoC for which the clock description should be
+ * @soc_type: The type of MPC83XX SoC for which the clock description should be
* retrieved
* @mode: Pointer to a clk_mode structure to be filled with data for the
* clock
*
- * Since some clock rate are stored in different places on different MPC83xx
+ * Since some clock rate are stored in different places on different MPC83XX
* SoCs, the SoC type has to be supplied along with the clock's identifier.
*
* Return: 0 if OK, -ve on error
@@ -269,7 +269,7 @@ static int retrieve_mode(int clk, int soc_type, struct clk_mode *mode)
/**
* get_spmr() - Read the SPMR (System PLL Mode Register)
- * @im: Pointer to the MPC83xx main register map in question
+ * @im: Pointer to the MPC83XX main register map in question
*
* Return: The SPMR value as a 32-bit number.
*/
@@ -282,7 +282,7 @@ static inline u32 get_spmr(immap_t *im)
/**
* get_sccr() - Read the SCCR (System Clock Control Register)
- * @im: Pointer to the MPC83xx main register map in question
+ * @im: Pointer to the MPC83XX main register map in question
*
* Return: The SCCR value as a 32-bit number.
*/
@@ -295,7 +295,7 @@ static inline u32 get_sccr(immap_t *im)
/**
* get_lcrr() - Read the LCRR (Clock Ratio Register)
- * @im: Pointer to the MPC83xx main register map in question
+ * @im: Pointer to the MPC83XX main register map in question
*
* Return: The LCRR value as a 32-bit number.
*/
@@ -308,7 +308,7 @@ static inline u32 get_lcrr(immap_t *im)
/**
* get_pci_sync_in() - Read the PCI synchronization clock speed
- * @im: Pointer to the MPC83xx main register map in question
+ * @im: Pointer to the MPC83XX main register map in question
*
* Return: The PCI synchronization clock speed value as a 32-bit number.
*/
@@ -322,7 +322,7 @@ static inline u32 get_pci_sync_in(immap_t *im)
/**
* get_csb_clk() - Read the CSB (Coheren System Bus) clock speed
- * @im: Pointer to the MPC83xx main register map in question
+ * @im: Pointer to the MPC83XX main register map in question
*
* Return: The CSB clock speed value as a 32-bit number.
*/
@@ -336,7 +336,7 @@ static inline u32 get_csb_clk(immap_t *im)
/**
* spmr_field() - Read a specific SPMR field
- * @im: Pointer to the MPC83xx main register map in question
+ * @im: Pointer to the MPC83XX main register map in question
* @mask: A bitmask that describes the bitfield to be read
*
* Return: The value of the bit field as a 32-bit number.
@@ -351,7 +351,7 @@ static inline uint spmr_field(immap_t *im, u32 mask)
/**
* sccr_field() - Read a specific SCCR field
- * @im: Pointer to the MPC83xx main register map in question
+ * @im: Pointer to the MPC83XX main register map in question
* @mask: A bitmask that describes the bitfield to be read
*
* Return: The value of the bit field as a 32-bit number.
@@ -366,7 +366,7 @@ static inline uint sccr_field(immap_t *im, u32 mask)
/**
* lcrr_field() - Read a specific LCRR field
- * @im: Pointer to the MPC83xx main register map in question
+ * @im: Pointer to the MPC83XX main register map in question
* @mask: A bitmask that describes the bitfield to be read
*
* Return: The value of the bit field as a 32-bit number.
@@ -8,11 +8,11 @@ config CPU
finding out information about available CPUs and making changes.
config CPU_MPC83XX
- bool "Enable MPC83xx CPU driver"
- depends on CPU && MPC83xx
+ bool "Enable MPC83XX CPU driver"
+ depends on CPU && MPC83XX
select CLK_MPC83XX
help
- Support CPU cores for SoCs of the MPC83xx series.
+ Support CPU cores for SoCs of the MPC83XX series.
config CPU_RISCV
bool "Enable RISC-V CPU driver"
@@ -16,10 +16,10 @@
#include "mpc83xx_cpu.h"
/**
- * struct mpc83xx_cpu_priv - Private data for MPC83xx CPUs
- * @e300_type: The e300 core type of the MPC83xx CPU
- * @family: The MPC83xx family the CPU belongs to
- * @type: The MPC83xx type of the CPU
+ * struct mpc83xx_cpu_priv - Private data for MPC83XX CPUs
+ * @e300_type: The e300 core type of the MPC83XX CPU
+ * @family: The MPC83XX family the CPU belongs to
+ * @type: The MPC83XX type of the CPU
* @is_e_processor: Flag indicating whether the CPU is a E processor or not
* @is_a_variant: Flag indicating whtther the CPU is a A variant or not
* @revid: The revision ID of the CPU
@@ -57,7 +57,7 @@ static inline u32 get_spridr(void)
}
/**
- * determine_type() - Determine CPU family of MPC83xx device
+ * determine_type() - Determine CPU family of MPC83XX device
* @dev: CPU device from which to read CPU family from
*/
static inline void determine_family(const struct udevice *dev)
@@ -92,7 +92,7 @@ static inline void determine_family(const struct udevice *dev)
}
/**
- * determine_type() - Determine CPU type of MPC83xx device
+ * determine_type() - Determine CPU type of MPC83XX device
* @dev: CPU device from which to read CPU type from
*/
static inline void determine_type(const struct udevice *dev)
@@ -166,7 +166,7 @@ static inline void determine_type(const struct udevice *dev)
}
/**
- * determine_e300_type() - Determine e300 core type of MPC83xx device
+ * determine_e300_type() - Determine e300 core type of MPC83XX device
* @dev: CPU device from which to read e300 core type from
*/
static inline void determine_e300_type(const struct udevice *dev)
@@ -33,14 +33,14 @@ static const char * const e300_names[] = {
};
/**
- * enum mpc83xx_cpu_family - Identifiers for MPC83xx CPU families
+ * enum mpc83xx_cpu_family - Identifiers for MPC83XX CPU families
* @FAMILY_830X: Identifier for the MPC830x CPU family
* @FAMILY_831X: Identifier for the MPC831x CPU family
* @FAMILY_832X: Identifier for the MPC832x CPU family
* @FAMILY_834X: Identifier for the MPC834x CPU family
* @FAMILY_836X: Identifier for the MPC836x CPU family
* @FAMILY_837X: Identifier for the MPC837x CPU family
- * @FAMILY_UNKNOWN: Identifier for an unknown MPC83xx CPU family
+ * @FAMILY_UNKNOWN: Identifier for an unknown MPC83XX CPU family
*/
enum mpc83xx_cpu_family {
FAMILY_830X,
@@ -53,7 +53,7 @@ enum mpc83xx_cpu_family {
};
/**
- * enum mpc83xx_cpu_type - Identifiers for MPC83xx CPU types
+ * enum mpc83xx_cpu_type - Identifiers for MPC83XX CPU types
* @TYPE_8308: Identifier for the MPC8308 CPU type
* @TYPE_8309: Identifier for the MPC8309 CPU type
* @TYPE_8311: Identifier for the MPC8311 CPU type
@@ -76,7 +76,7 @@ enum mpc83xx_cpu_family {
* @TYPE_8377: Identifier for the MPC8377 CPU type
* @TYPE_8378: Identifier for the MPC8378 CPU type
* @TYPE_8379: Identifier for the MPC8379 CPU type
- * @TYPE_UNKNOWN: Identifier for an unknown MPC83xx CPU type
+ * @TYPE_UNKNOWN: Identifier for an unknown MPC83XX CPU type
*/
enum mpc83xx_cpu_type {
TYPE_8308,
@@ -173,7 +173,7 @@ config DDR_ECC
config DDR_ECC_CMD
bool "Access the ECC features of the memory controller"
- depends on DDR_ECC && MPC83xx
+ depends on DDR_ECC && MPC83XX
default y
config ECC_INIT_VIA_DDRCONTROLLER
@@ -199,7 +199,7 @@ config SYS_FSL_DDR_INTLV_256B
endif
menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
- depends on MCF52x2 || MPC8xx || MPC83xx || MPC85xx
+ depends on MCF52x2 || MPC8xx || MPC83XX || MPC85xx
config SYS_BR0_PRELIM_BOOL
bool "Define Bank 0"
@@ -29,7 +29,7 @@
* 0x80_8000_0000 ~ 0xff_ffff_ffff
*/
#ifndef CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
-#ifdef CONFIG_MPC83xx
+#ifdef CONFIG_MPC83XX
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_SDRAM_BASE
#else
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_DDR_SDRAM_BASE
@@ -16,15 +16,15 @@
/* Controller can only transfer 2^26 - 1 bytes at a time */
#define FSL_DMA_MAX_SIZE (0x3ffffff)
-#if defined(CONFIG_MPC83xx)
+#if defined(CONFIG_MPC83XX)
#define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_CTM_DIRECT | FSL_DMA_MR_DMSEN)
#else
#define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT)
#endif
-#if defined(CONFIG_MPC83xx)
-dma83xx_t *dma_base = (void *)(CFG_SYS_MPC83xx_DMA_ADDR);
+#if defined(CONFIG_MPC83XX)
+dma83xx_t *dma_base = (void *)(CFG_SYS_MPC83XX_DMA_ADDR);
#elif defined(CONFIG_MPC85xx)
ccsr_dma_t *dma_base = (void *)(CFG_SYS_MPC85xx_DMA_ADDR);
#elif defined(CONFIG_MPC86xx)
@@ -44,7 +44,7 @@ static void dma_sync(void)
static void out_dma32(volatile unsigned *addr, int val)
{
-#if defined(CONFIG_MPC83xx)
+#if defined(CONFIG_MPC83XX)
out_le32(addr, val);
#else
out_be32(addr, val);
@@ -53,7 +53,7 @@ static void out_dma32(volatile unsigned *addr, int val)
static uint in_dma32(volatile unsigned *addr)
{
-#if defined(CONFIG_MPC83xx)
+#if defined(CONFIG_MPC83XX)
return in_le32(addr);
#else
return in_be32(addr);
@@ -79,7 +79,7 @@ static uint dma_check(void) {
return status;
}
-#if !defined(CONFIG_MPC83xx)
+#if !defined(CONFIG_MPC83XX)
void dma_init(void) {
volatile fsl_dma_t *dma = &dma_base->dma[0];
@@ -99,7 +99,7 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF));
out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF));
-#if !defined(CONFIG_MPC83xx)
+#if !defined(CONFIG_MPC83XX)
out_dma32(&dma->satr,
in_dma32(&dma->satr) | (u32)((u64)src >> 32));
out_dma32(&dma->datr,
@@ -131,7 +131,7 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
/*
* 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER
*/
-#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \
+#if ((!defined CONFIG_MPC83XX && defined(CONFIG_DDR_ECC) && \
!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)))
void dma_meminit(uint size)
{
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Freescale MPC83xx GPIO handling.
+ * Freescale MPC83XX GPIO handling.
*/
#include <common.h>
@@ -581,10 +581,10 @@ config GDSYS_IOEP
Support gdsys FPGA's IO endpoint driver.
config MPC83XX_SERDES
- bool "Enable MPC83xx serdes driver"
+ bool "Enable MPC83XX serdes driver"
depends on MISC
help
- Support for serdes found on MPC83xx SoCs.
+ Support for serdes found on MPC83XX SoCs.
config FS_LOADER
bool "Enable loader driver for file system"
@@ -3,7 +3,7 @@
* (C) Copyright 2018
* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
*
- * base on the MPC83xx serdes initialization, which is
+ * base on the MPC83XX serdes initialization, which is
*
* Copyright 2007,2011 Freescale Semiconductor, Inc.
* Copyright (C) 2008 MontaVista Software, Inc.
@@ -19,7 +19,7 @@
#include "mpc83xx_serdes.h"
/**
- * struct mpc83xx_serdes_priv - Private structure for MPC83xx serdes
+ * struct mpc83xx_serdes_priv - Private structure for MPC83XX serdes
* @regs: The device's register map
* @rfcks: Variable to keep the serdes reference clock selection set during
* initialization in (is or'd to every value written to SRDSCR4)
@@ -16,7 +16,7 @@
#include <asm/fsl_lbc.h>
#include <nand.h>
-#ifdef CONFIG_MPC83xx
+#ifdef CONFIG_MPC83XX
#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
#endif
@@ -38,7 +38,7 @@ config MPC83XX_SDRAM
bool "Enable MPC83XX SDRAM support"
depends on RAM
help
- Enable support for the internal DDR Memory Controller of the MPC83xx
+ Enable support for the internal DDR Memory Controller of the MPC83XX
family of SoCs. Both static configurations, as well as configuring
the RAM through the use of SPD (Serial Presence Detect) is supported
via device tree settings.
@@ -122,7 +122,7 @@ phys_size_t get_effective_memsize(void)
}
/**
- * struct mpc83xx_sdram_priv - Private data for MPC83xx RAM controllers
+ * struct mpc83xx_sdram_priv - Private data for MPC83XX RAM controllers
* @total_size: The total size of all RAM modules associated with this RAM
* controller in bytes
*/
@@ -84,7 +84,7 @@ static int mpc8xxx_spi_probe(struct udevice *dev)
spi8xxx_t *spi = priv->spi;
/*
- * SPI pins on the MPC83xx are not muxed, so all we do is initialize
+ * SPI pins on the MPC83XX are not muxed, so all we do is initialize
* some registers
*/
out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS);
@@ -189,9 +189,9 @@ config SYSRESET_TPL_X86
Reboot support for generic x86 processor reset in TPL.
config SYSRESET_MPC83XX
- bool "Enable support MPC83xx SoC family reboot driver"
+ bool "Enable support MPC83XX SoC family reboot driver"
help
- Reboot support for NXP MPC83xx SoCs.
+ Reboot support for NXP MPC83XX SoCs.
endif
@@ -153,11 +153,11 @@ config GXP_TIMER
present on HPE GXP SoCs.
config MPC83XX_TIMER
- bool "MPC83xx timer support"
+ bool "MPC83XX timer support"
depends on TIMER
help
Select this to enable support for the timer found on
- devices based on the MPC83xx family of SoCs.
+ devices based on the MPC83XX family of SoCs.
config RENESAS_OSTM_TIMER
bool "Renesas RZ/A1 R7S72100 OSTM Timer"
@@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
/**
- * struct mpc83xx_timer_priv - Private data structure for MPC83xx timer driver
+ * struct mpc83xx_timer_priv - Private data structure for MPC83XX timer driver
* @decrementer_count: Value to which the decrementer register should be re-set
* to when a timer interrupt occurs, thus determines the
* interrupt frequency (value for 1e6/HZ microseconds)
@@ -116,7 +116,7 @@ config ENV_IS_IN_FLASH
default y if ARCH_INTEGRATOR_CP
default y if M548x || M547x || M5282
default y if MCF532X || MCF52x2
- default y if MPC86xx || MPC83xx
+ default y if MPC86xx || MPC83XX
default y if ARCH_MPC8548
default y if SH && !CPU_SH4
help
@@ -43,7 +43,7 @@ struct bd_info {
#if defined(CONFIG_M68K)
unsigned long bi_mbar_base; /* base of internal registers */
#endif
-#if defined(CONFIG_MPC83xx)
+#if defined(CONFIG_MPC83XX)
unsigned long bi_immrbar;
#endif
unsigned long bi_bootflags; /* boot / reboot flag (Unused) */
@@ -175,7 +175,7 @@
#define CFG_SYS_PCIE2_IO_PHYS 0xD8000000
#ifdef CONFIG_MMC
-#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83XX_ESDHC_ADDR
#endif
/*
@@ -11,7 +11,7 @@
#ifndef __IMMAP_QE_H__
#define __IMMAP_QE_H__
-#ifdef CONFIG_MPC83xx
+#ifdef CONFIG_MPC83XX
#if defined(CONFIG_ARCH_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#define MAX_QE_RISC 2
@@ -27,7 +27,7 @@ extern struct serial_device serial_smh_device;
extern struct serial_device serial_scc_device;
extern struct serial_device *default_serial_console(void);
-#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
+#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || \
defined(CONFIG_ARCH_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \
defined(CONFIG_MICROBLAZE)
@@ -8,4 +8,4 @@ obj-y += tests.o
obj-y += drivers/
obj-$(CONFIG_PPC) += lib_powerpc/
-obj-$(CONFIG_MPC83xx) += cpu/mpc83xx/
+obj-$(CONFIG_MPC83XX) += cpu/mpc83xx/