diff mbox series

[u-boot,v2,3/3] arm: dts: k3-am64: Fix CPSW3G ethernet

Message ID 20230124094327.46394-4-rogerq@kernel.org
State Accepted
Commit 4599bb7d79463da7e53b8920c759ad2a172ae2a5
Delegated to: Tom Rini
Headers show
Series arm: dts: k3-am64: Sync DT files with Linux | expand

Commit Message

Roger Quadros Jan. 24, 2023, 9:43 a.m. UTC 
As MDIO driver does not support Driver Model, the
pinctrl settings in the MDIO node will not
be applied resulting in PHY not being detected.

To workaround this we add the MDIO pinctrl in
the CPSW3G node in the -u-boot.dtsi file.

Add the missing MDIO and RGMII pinctrl nodes in
k3-am642-r5-evm.dts

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 arch/arm/dts/k3-am642-evm-u-boot.dtsi |  3 ++
 arch/arm/dts/k3-am642-r5-evm.dts      | 41 +++++++++++++++++++++++++++
 2 files changed, 44 insertions(+)

Comments

Tom Rini Jan. 24, 2023, 7:19 p.m. UTC | #1 
On Tue, Jan 24, 2023 at 11:43:27AM +0200, Roger Quadros wrote:

> As MDIO driver does not support Driver Model, the
> pinctrl settings in the MDIO node will not
> be applied resulting in PHY not being detected.
> 
> To workaround this we add the MDIO pinctrl in
> the CPSW3G node in the -u-boot.dtsi file.
> 
> Add the missing MDIO and RGMII pinctrl nodes in
> k3-am642-r5-evm.dts
> 
> Signed-off-by: Roger Quadros <rogerq@kernel.org>

Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini Feb. 7, 2023, 4:49 p.m. UTC | #2 
On Tue, Jan 24, 2023 at 11:43:27AM +0200, Roger Quadros wrote:

> As MDIO driver does not support Driver Model, the
> pinctrl settings in the MDIO node will not
> be applied resulting in PHY not being detected.
> 
> To workaround this we add the MDIO pinctrl in
> the CPSW3G node in the -u-boot.dtsi file.
> 
> Add the missing MDIO and RGMII pinctrl nodes in
> k3-am642-r5-evm.dts
> 
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
index fa7750d634f..9b6c7e85cb4 100644
--- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
@@ -113,6 +113,9 @@ 
 	      <0x0 0x43000200 0x0 0x8>;
 	reg-names = "cpsw_nuss", "mac_efuse";
 	/delete-property/ ranges;
+	pinctrl-0 = <&mdio1_pins_default	/* HACK: as MDIO driver is not DM enabled */
+		     &rgmii1_pins_default
+		     &rgmii2_pins_default>;
 
 	cpsw-phy-sel@04044 {
 		compatible = "ti,am64-phy-gmii-sel";
diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts
index 92a6bfdc011..7493362ac65 100644
--- a/arch/arm/dts/k3-am642-r5-evm.dts
+++ b/arch/arm/dts/k3-am642-r5-evm.dts
@@ -167,6 +167,47 @@ 
 			AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
 		>;
 	};
+
+	mdio1_pins_default: mdio1-pins-default {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
+			AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
+		>;
+	};
+
+	rgmii1_pins_default: rgmii1-pins-default {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
+			AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
+			AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
+			AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
+			AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
+			AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
+			AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
+			AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
+			AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
+			AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
+			AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
+			AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
+		>;
+	};
+
+       rgmii2_pins_default: rgmii2-pins-default {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
+			AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
+			AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
+			AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
+			AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
+			AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
+			AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
+			AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
+			AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
+			AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
+			AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
+			AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
+		>;
+	};
 };
 
 &dmsc {