diff mbox series

[v3,1/2] riscv: ax25: bypass malloc when spl fit boots from ram

Message ID 20230104015543.29733-1-rick@andestech.com
State Accepted
Commit 5b71b7bf92dd12dfb768180fc25ab4616f077642
Delegated to: Andes
Headers show
Series [v3,1/2] riscv: ax25: bypass malloc when spl fit boots from ram | expand

Commit Message

Rick Chen Jan. 4, 2023, 1:55 a.m. UTC
When fit image boots from ram, the payload will
be prepared in the address of SPL_LOAD_FIT_ADDRESS.
In spl fit generic flow, it will malloc another
memory address and copy whole fit image to this
malloc address.  But it is un-necessary for booting
from RAM.

This patch improves this flow by declare the
board_spl_fit_buffer_addr() to replace the original one.
The larger image size (eq: Kernel Image 10~20MB), it
can save more booting time.

Signed-off-by: Rick Chen <rick@andestech.com>
---
Changes in v3
 - fix aligment
 - refine board_spl_fit_buffer_addr
---
 arch/riscv/cpu/ax25/Makefile |  1 +
 arch/riscv/cpu/ax25/spl.c    | 27 +++++++++++++++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 arch/riscv/cpu/ax25/spl.c

Comments

Leo Liang Jan. 31, 2023, 2:59 p.m. UTC | #1
On Wed, Jan 04, 2023 at 09:55:43AM +0800, Rick Chen wrote:
> When fit image boots from ram, the payload will
> be prepared in the address of SPL_LOAD_FIT_ADDRESS.
> In spl fit generic flow, it will malloc another
> memory address and copy whole fit image to this
> malloc address.  But it is un-necessary for booting
> from RAM.
> 
> This patch improves this flow by declare the
> board_spl_fit_buffer_addr() to replace the original one.
> The larger image size (eq: Kernel Image 10~20MB), it
> can save more booting time.
> 
> Signed-off-by: Rick Chen <rick@andestech.com>
> ---
> Changes in v3
>  - fix aligment
>  - refine board_spl_fit_buffer_addr
> ---
>  arch/riscv/cpu/ax25/Makefile |  1 +
>  arch/riscv/cpu/ax25/spl.c    | 27 +++++++++++++++++++++++++++
>  2 files changed, 28 insertions(+)
>  create mode 100644 arch/riscv/cpu/ax25/spl.c
> 
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff mbox series

Patch

diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Makefile
index 318baccb09..35a1a2fb83 100644
--- a/arch/riscv/cpu/ax25/Makefile
+++ b/arch/riscv/cpu/ax25/Makefile
@@ -5,3 +5,4 @@ 
 
 obj-y	:= cpu.o
 obj-y	+= cache.o
+obj-y	+= spl.o
diff --git a/arch/riscv/cpu/ax25/spl.c b/arch/riscv/cpu/ax25/spl.c
new file mode 100644
index 0000000000..413849043b
--- /dev/null
+++ b/arch/riscv/cpu/ax25/spl.c
@@ -0,0 +1,27 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/system.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if CONFIG_IS_ENABLED(RAM_SUPPORT)
+struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
+{
+	return (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + offset);
+}
+
+void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
+{
+	return spl_get_load_buffer(0, sectors * bl_len);
+}
+#endif