diff mbox series

[4/6] arm: dts: socfpga: Update existing FW & SEC config to DTS

Message ID 20221211130644.24832-4-jit.loon.lim@intel.com
State Needs Review / ACK, archived
Delegated to: Marek Vasut
Headers show
Series [1/6] doc: dtbinding: Add doc for privilege regs settings | expand

Commit Message

Jit Loon Lim Dec. 11, 2022, 1:06 p.m. UTC 
From: Tien Fong Chee <tien.fong.chee@intel.com>

Update N5X existing firewall and secure register settings in source codes to
device tree.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
 arch/arm/dts/socfpga_n5x-u-boot.dtsi | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
index 98cbd4c808..c25d99366a 100644
--- a/arch/arm/dts/socfpga_n5x-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
@@ -132,6 +132,8 @@ 
 &spi1 {
 	clocks = <&clkmgr N5X_L4_MAIN_CLK>;
 
+};
+
 &socfpga_secreg {
 	soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 {
 		reg = <0xf8020000 0x0000001c>;