From patchwork Sun Dec 11 13:06:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1714601 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=kijU0yx9; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NVQ6V6Jgnz23np for ; Mon, 12 Dec 2022 00:08:02 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4575D853B3; Sun, 11 Dec 2022 14:07:18 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kijU0yx9"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id E9B5C8538D; Sun, 11 Dec 2022 14:07:07 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7AAA8853AA for ; Sun, 11 Dec 2022 14:06:56 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670764016; x=1702300016; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9gobqB0QIqWKgBPDSuB6xo7wAliPN/zF1x1XeiB/3Jk=; b=kijU0yx9yD9sO784MXEfKgekQ8Ji2PHIAK2EoJjiaBLg0fawQGivq0Bu VKIHfCeYsizeWcJjVIkgpHcsW6F50dxfyYIcOiT8x4MvmtDXsI/zsJdT6 PpIquOh2UqBxs4WOvvbqkATr916C8u4/OrzAkOmobsG8MGbKNTvEpXjfX e+IC8KCw0p0fq00CGFLBoYGCXUUe+3uCs7lR35hsAea2UNexaZxaKw9fA swLGb0iL8DJlZuwOZ17v5wUNL2HoHIJa53BmcdbFXVbJ++3aZFgV/x1Fu Ud4mVpD4NlFltb145rlcyEov3pqoh10D6qrNSDLDaTuF1etPWZ3GhslYC Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10557"; a="316394352" X-IronPort-AV: E=Sophos;i="5.96,236,1665471600"; d="scan'208";a="316394352" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2022 05:06:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10557"; a="678625513" X-IronPort-AV: E=Sophos;i="5.96,236,1665471600"; d="scan'208";a="678625513" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga008.jf.intel.com with ESMTP; 11 Dec 2022 05:06:48 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id DE1842706; Sun, 11 Dec 2022 21:06:47 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id DB0FCE0095A; Sun, 11 Dec 2022 21:06:47 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang Subject: [PATCH 3/6] arm: dts: socfpga: Copy existing FW & SEC config to DTS Date: Sun, 11 Dec 2022 21:06:41 +0800 Message-Id: <20221211130644.24832-3-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20221211130644.24832-1-jit.loon.lim@intel.com> References: <20221211130644.24832-1-jit.loon.lim@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Copy existing firewall and secure register settings in source codes to device tree. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- arch/arm/dts/socfpga_agilex-u-boot.dtsi | 13 ++- arch/arm/dts/socfpga_n5x-u-boot.dtsi | 10 ++ arch/arm/dts/socfpga_soc64_u-boot.dtsi | 112 +++++++++++++++++++++ arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 17 +++- 4 files changed, 150 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi index 08f7cf7f7a..774cebd30c 100644 --- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi @@ -2,9 +2,10 @@ /* * U-Boot additions * - * Copyright (C) 2019-2020 Intel Corporation + * Copyright (C) 2019-2021 Intel Corporation */ +#include "socfpga_soc64_u-boot.dtsi" #include "socfpga_soc64_fit-u-boot.dtsi" /{ @@ -84,6 +85,16 @@ u-boot,dm-pre-reloc; }; +&socfpga_secreg { + soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { + reg = <0xf8020000 0x0000001c>; + intel,offset-settings = + <0x00000000 0x00010101>, + <0x00000004 0x00000001>; + u-boot,dm-pre-reloc; + }; +}; + &sysmgr { compatible = "altr,sys-mgr", "syscon"; u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi b/arch/arm/dts/socfpga_n5x-u-boot.dtsi index d377ae5f69..98cbd4c808 100644 --- a/arch/arm/dts/socfpga_n5x-u-boot.dtsi +++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2020-2021 Intel Corporation */ +#include "socfpga_soc64_u-boot.dtsi" #include "socfpga_soc64_fit-u-boot.dtsi" #include @@ -130,6 +131,15 @@ &spi1 { clocks = <&clkmgr N5X_L4_MAIN_CLK>; + +&socfpga_secreg { + soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { + reg = <0xf8020000 0x0000001c>; + intel,offset-settings = + <0x00000000 0x00010101>, + <0x00000004 0x00000001>; + u-boot,dm-pre-reloc; + }; }; &sysmgr { diff --git a/arch/arm/dts/socfpga_soc64_u-boot.dtsi b/arch/arm/dts/socfpga_soc64_u-boot.dtsi new file mode 100644 index 0000000000..34997b4c30 --- /dev/null +++ b/arch/arm/dts/socfpga_soc64_u-boot.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2021 Intel Corporation + */ + +/ { + soc { + socfpga_secreg: socfpga-secreg { + compatible = "intel,socfpga-secreg"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + i_sys_mgr_core@ffd12000 { + reg = <0xffd12000 0x00000230>; + intel,offset-settings = + <0x00000020 0xff010000>, + <0x00000024 0xffffffff>; + u-boot,dm-pre-reloc; + }; + + noc_fw_l4_per_l4_per_scr@ffd21000 { + reg = <0xffd21000 0x00000074>; + intel,offset-settings = + <0x00000000 0x01010001>, + <0x00000004 0x01010001>, + <0x0000000c 0x01010001>, + <0x00000010 0x01010001>, + <0x0000001c 0x01010001>, + <0x00000020 0x01010001>, + <0x00000024 0x01010001>, + <0x00000028 0x01010001>, + <0x0000002c 0x01010001>, + <0x00000030 0x01010001>, + <0x00000034 0x01010001>, + <0x00000040 0x01010001>, + <0x00000044 0x01010001>, + <0x00000048 0x01010001>, + <0x00000050 0x01010001>, + <0x00000054 0x01010001>, + <0x00000058 0x01010001>, + <0x0000005c 0x01010001>, + <0x00000060 0x01010001>, + <0x00000064 0x01010001>, + <0x00000068 0x01010001>, + <0x0000006c 0x01010001>, + <0x00000070 0x01010001>; + u-boot,dm-pre-reloc; + }; + + noc_fw_l4_sys_l4_sys_scr@ffd21100 { + reg = <0xffd21100 0x00000098>; + intel,offset-settings = + <0x00000008 0x01010001>, + <0x0000000c 0x01010001>, + <0x00000010 0x01010001>, + <0x00000014 0x01010001>, + <0x00000018 0x01010001>, + <0x0000001c 0x01010001>, + <0x00000020 0x01010001>, + <0x0000002c 0x01010001>, + <0x00000030 0x01010001>, + <0x00000034 0x01010001>, + <0x00000038 0x01010001>, + <0x00000040 0x01010001>, + <0x00000044 0x01010001>, + <0x00000048 0x01010001>, + <0x0000004c 0x01010001>, + <0x00000054 0x01010001>, + <0x00000058 0x01010001>, + <0x0000005c 0x01010001>, + <0x00000060 0x01010001>, + <0x00000064 0x01010001>, + <0x00000068 0x01010001>, + <0x0000006c 0x01010001>, + <0x00000070 0x01010001>, + <0x00000074 0x01010001>, + <0x00000078 0x01010001>, + <0x00000090 0x01010001>, + <0x00000094 0x01010001>; + u-boot,dm-pre-reloc; + }; + + noc_fw_soc2fpga_soc2fpga_scr@ffd21200 { + reg = <0xffd21200 0x00000004>; + intel,offset-settings = <0x00000000 0x0ffe0101>; + u-boot,dm-pre-reloc; + }; + + noc_fw_lwsoc2fpga_lwsoc2fpga_scr@ffd21300 { + reg = <0xffd21300 0x00000004>; + intel,offset-settings = <0x00000000 0x0ffe0101>; + u-boot,dm-pre-reloc; + }; + + noc_fw_tcu_tcu_scr@ffd21400 { + reg = <0xffd21400 0x00000004>; + intel,offset-settings = <0x00000000 0x01010001>; + u-boot,dm-pre-reloc; + }; + + noc_fw_priv_MemoryMap_priv@ffd24800 { + reg = <0xffd24800 0x0000000c>; + intel,offset-settings = + <0x00000000 0xfff73ffb>; + u-boot,dm-pre-reloc; + }; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi index 3e3a378046..577cbf9770 100644 --- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi @@ -2,7 +2,22 @@ /* * U-Boot additions * - * Copyright (C) 2020 Intel Corporation + * Copyright (C) 2020-2021 Intel Corporation */ +#include "socfpga_soc64_u-boot.dtsi" #include "socfpga_soc64_fit-u-boot.dtsi" + +&socfpga_secreg { + i_ccu_noc_registers@f7000000 { + reg = <0xf7000000 0x00049e60>; + intel,offset-settings = + <0x000105a0 0x00000000>, + <0x000105c0 0x00000000>, + <0x000105e0 0x00000000>, + <0x00010600 0x00000000>, + <0x00010620 0x00000000>, + <0x00010640 0x00000000>; + u-boot,dm-pre-reloc; + }; +};