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[1/6] doc: dtbinding: Add doc for privilege regs settings

Message ID 20221211130644.24832-1-jit.loon.lim@intel.com
State Needs Review / ACK, archived
Delegated to: Marek Vasut
Headers show
Series [1/6] doc: dtbinding: Add doc for privilege regs settings | expand

Commit Message

Jit Loon Lim Dec. 11, 2022, 1:06 p.m. UTC 
From: Tien Fong Chee <tien.fong.chee@intel.com>

Add a document to describe firewall and privilege register settings binding
information.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
 .../misc/socfpga_secreg.txt                   | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 doc/device-tree-bindings/misc/socfpga_secreg.txt
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Patch

diff --git a/doc/device-tree-bindings/misc/socfpga_secreg.txt b/doc/device-tree-bindings/misc/socfpga_secreg.txt
new file mode 100644
index 0000000000..66df51f613
--- /dev/null
+++ b/doc/device-tree-bindings/misc/socfpga_secreg.txt
@@ -0,0 +1,26 @@ 
+* Firewall and privilege register settings in device tree
+
+Required properties:
+--------------------
+
+- compatible: should contain "intel,socfpga-secreg"
+- intel,offset-settings: 32-bit offset address of block register, and then
+						 followed by 32-bit value settings.
+
+Example:
+--------
+
+		socfpga_secreg: socfpga-secreg {
+			compatible = "intel,socfpga-secreg";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			u-boot,dm-pre-reloc;
+
+			i_sys_mgr@ffd12000 {
+				reg = <0xffd12000 0x00000228>;
+				intel,offset-settings =
+					<0x00000020 0xff010000>,
+					<0x00000024 0xffffffff>;
+				u-boot,dm-pre-reloc;
+			};
+		};