From patchwork Tue Dec 6 00:45:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1712481 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NR1x52Sjsz23ys for ; Tue, 6 Dec 2022 11:48:09 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 078B585358; Tue, 6 Dec 2022 01:47:42 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 0A72285324; Tue, 6 Dec 2022 01:47:36 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 0AC0885317 for ; Tue, 6 Dec 2022 01:47:29 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2ABDDD6E; Mon, 5 Dec 2022 16:47:35 -0800 (PST) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 591C83F73B; Mon, 5 Dec 2022 16:47:27 -0800 (PST) From: Andre Przywara To: Samuel Holland , Jagan Teki Cc: u-boot@lists.denx.de, Icenowy Zheng , Jernej Skrabec Subject: [RFC PATCH 03/17] pinctrl: sunxi: remove struct sunxi_gpio Date: Tue, 6 Dec 2022 00:45:35 +0000 Message-Id: <20221206004549.29015-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.5 In-Reply-To: <20221206004549.29015-1-andre.przywara@arm.com> References: <20221206004549.29015-1-andre.przywara@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean So far every Allwinner SoC used the same basic pincontroller/GPIO register frame, and just differed by the number of implemented banks and pins, plus some special functionality from time to time. However the D1 and successors use a slightly different pinctrl register layout. Use that opportunity to drop "struct sunxi_gpio", that described that MMIO frame in a C struct. That approach is somewhat frowned upon in the Linux world and rarely used there, though still popular with U-Boot. Switching from a C struct to a "base address plus offset" approach allows to switch between the two models more dynamically, without reverting to preprocessor macros and #ifdef's. Model the pinctrl MMIO register frame in the usual "base address + offset" way, and replace a hard-to-parse CPP macro with a more readable static function. All the users get converted over. There are no functional changes at this point, it just prepares the stages for the D1 and friends. Signed-off-by: Andre Przywara --- arch/arm/include/asm/arch-sunxi/gpio.h | 63 +++++++++++--------------- arch/arm/mach-sunxi/pinmux.c | 51 +++++++++++---------- drivers/gpio/sunxi_gpio.c | 15 +++--- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 14 +++--- 4 files changed, 68 insertions(+), 75 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 437e86479ce..8333810a69f 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -28,13 +28,6 @@ #define SUNXI_GPIO_H 7 #define SUNXI_GPIO_I 8 -/* - * This defines the number of GPIO banks for the _main_ GPIO controller. - * You should fix up the padding in struct sunxi_gpio_reg below if you - * change this. - */ -#define SUNXI_GPIO_BANKS 9 - /* * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO) * at a different register offset. @@ -52,46 +45,42 @@ #define SUNXI_GPIO_M 12 #define SUNXI_GPIO_N 13 -struct sunxi_gpio { - u32 cfg[4]; - u32 dat; - u32 drv[2]; - u32 pull[2]; -}; - -/* gpio interrupt control */ -struct sunxi_gpio_int { - u32 cfg[3]; - u32 ctl; - u32 sta; - u32 deb; /* interrupt debounce */ -}; - -struct sunxi_gpio_reg { - struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS]; - u8 res[0xbc]; - struct sunxi_gpio_int gpio_int; -}; - #define SUN50I_H6_GPIO_POW_MOD_SEL 0x340 #define SUN50I_H6_GPIO_POW_MOD_VAL 0x348 -#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \ - &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ - &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L]) - #define GPIO_BANK(pin) ((pin) >> 5) #define GPIO_NUM(pin) ((pin) & 0x1f) +#define GPIO_CFG_REG_OFFSET 0x00 #define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3) #define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2) +#define GPIO_DAT_REG_OFFSET 0x10 + +#define GPIO_DRV_REG_OFFSET 0x14 #define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4) #define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) +#define GPIO_PULL_REG_OFFSET 0x1c #define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4) #define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) +#define SUNXI_PINCTRL_BANK_SIZE 0x24 + +static inline void* BANK_TO_GPIO(int bank) +{ + void *pio_base; + + if (bank < SUNXI_GPIO_L) { + pio_base = (void *)(uintptr_t)SUNXI_PIO_BASE; + } else { + pio_base = (void *)(uintptr_t)SUNXI_R_PIO_BASE; + bank -= SUNXI_GPIO_L; + } + + return pio_base + bank * SUNXI_PINCTRL_BANK_SIZE; +} + /* GPIO bank sizes */ #define SUNXI_GPIOS_PER_BANK 32 @@ -214,18 +203,18 @@ enum sunxi_gpio_number { #define SUNXI_GPIO_AXP0_GPIO_COUNT 6 struct sunxi_gpio_plat { - struct sunxi_gpio *regs; + void *regs; char bank_name[3]; }; -void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val); +void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val); void sunxi_gpio_set_cfgpin(u32 pin, u32 val); -int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); +int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset); int sunxi_gpio_get_cfgpin(u32 pin); void sunxi_gpio_set_drv(u32 pin, u32 val); -void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val); +void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val); void sunxi_gpio_set_pull(u32 pin, u32 val); -void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val); +void sunxi_gpio_set_pull_bank(void *bank_base, int pin_offset, u32 val); int sunxi_name_to_gpio(const char *name); #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c index c95fcee9f6c..b650f6b1aea 100644 --- a/arch/arm/mach-sunxi/pinmux.c +++ b/arch/arm/mach-sunxi/pinmux.c @@ -9,29 +9,30 @@ #include #include -void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val) +void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val) { - u32 index = GPIO_CFG_INDEX(bank_offset); - u32 offset = GPIO_CFG_OFFSET(bank_offset); + u32 index = GPIO_CFG_INDEX(pin_offset); + u32 offset = GPIO_CFG_OFFSET(pin_offset); - clrsetbits_le32(&pio->cfg[index], 0xf << offset, val << offset); + clrsetbits_le32(bank_base + GPIO_CFG_REG_OFFSET + index * 4, + 0xfU << offset, val << offset); } void sunxi_gpio_set_cfgpin(u32 pin, u32 val) { u32 bank = GPIO_BANK(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + void *pio = BANK_TO_GPIO(bank); - sunxi_gpio_set_cfgbank(pio, pin, val); + sunxi_gpio_set_cfgbank(pio, pin % 32, val); } -int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset) +int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset) { - u32 index = GPIO_CFG_INDEX(bank_offset); - u32 offset = GPIO_CFG_OFFSET(bank_offset); + u32 index = GPIO_CFG_INDEX(pin_offset); + u32 offset = GPIO_CFG_OFFSET(pin_offset); u32 cfg; - cfg = readl(&pio->cfg[index]); + cfg = readl(bank_base + GPIO_CFG_REG_OFFSET + index * 4); cfg >>= offset; return cfg & 0xf; @@ -40,39 +41,41 @@ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset) int sunxi_gpio_get_cfgpin(u32 pin) { u32 bank = GPIO_BANK(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + void *bank_base = BANK_TO_GPIO(bank); - return sunxi_gpio_get_cfgbank(pio, pin); + return sunxi_gpio_get_cfgbank(bank_base, pin % 32); } void sunxi_gpio_set_drv(u32 pin, u32 val) { u32 bank = GPIO_BANK(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + void *bank_base = BANK_TO_GPIO(bank); - sunxi_gpio_set_drv_bank(pio, pin, val); + sunxi_gpio_set_drv_bank(bank_base, pin % 32, val); } -void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val) +void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val) { - u32 index = GPIO_DRV_INDEX(bank_offset); - u32 offset = GPIO_DRV_OFFSET(bank_offset); + u32 index = GPIO_DRV_INDEX(pin_offset); + u32 offset = GPIO_DRV_OFFSET(pin_offset); - clrsetbits_le32(&pio->drv[index], 0x3 << offset, val << offset); + clrsetbits_le32(bank_base + GPIO_DRV_REG_OFFSET + index * 4, + 0x3U << offset, val << offset); } void sunxi_gpio_set_pull(u32 pin, u32 val) { u32 bank = GPIO_BANK(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + void *bank_base = BANK_TO_GPIO(bank); - sunxi_gpio_set_pull_bank(pio, pin, val); + sunxi_gpio_set_pull_bank(bank_base, pin % 32, val); } -void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val) +void sunxi_gpio_set_pull_bank(void *bank_base, int pin_offset, u32 val) { - u32 index = GPIO_PULL_INDEX(bank_offset); - u32 offset = GPIO_PULL_OFFSET(bank_offset); + u32 index = GPIO_PULL_INDEX(pin_offset); + u32 offset = GPIO_PULL_OFFSET(pin_offset); - clrsetbits_le32(&pio->pull[index], 0x3 << offset, val << offset); + clrsetbits_le32(bank_base + GPIO_PULL_REG_OFFSET + index * 4, + 0x3U << offset, val << offset); } diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index 1e85db179a6..1bf691a204a 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -24,15 +24,15 @@ static int sunxi_gpio_output(u32 pin, u32 val) u32 dat; u32 bank = GPIO_BANK(pin); u32 num = GPIO_NUM(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + void *pio = BANK_TO_GPIO(bank); - dat = readl(&pio->dat); + dat = readl(pio + 0x10); if (val) dat |= 0x1 << num; else dat &= ~(0x1 << num); - writel(dat, &pio->dat); + writel(dat, pio + 0x10); return 0; } @@ -42,9 +42,9 @@ static int sunxi_gpio_input(u32 pin) u32 dat; u32 bank = GPIO_BANK(pin); u32 num = GPIO_NUM(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + void *pio = BANK_TO_GPIO(bank); - dat = readl(&pio->dat); + dat = readl(pio + 0x10); dat >>= num; return dat & 0x1; @@ -138,7 +138,7 @@ static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset) u32 num = GPIO_NUM(offset); unsigned dat; - dat = readl(&plat->regs->dat); + dat = readl(plat->regs + GPIO_DAT_REG_OFFSET); dat >>= num; return dat & 0x1; @@ -181,7 +181,8 @@ static int sunxi_gpio_set_flags(struct udevice *dev, unsigned int offset, u32 value = !!(flags & GPIOD_IS_OUT_ACTIVE); u32 num = GPIO_NUM(offset); - clrsetbits_le32(&plat->regs->dat, 1 << num, value << num); + clrsetbits_le32(plat->regs + GPIO_DAT_REG_OFFSET, + 1 << num, value << num); sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT); } else if (flags & GPIOD_IS_IN) { u32 pull = 0; diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 061104be056..5ab3951ab52 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -35,7 +35,7 @@ struct sunxi_pinctrl_desc { }; struct sunxi_pinctrl_plat { - struct sunxi_gpio __iomem *base; + void __iomem *base; }; static int sunxi_pinctrl_get_pins_count(struct udevice *dev) @@ -86,8 +86,8 @@ static int sunxi_pinctrl_pinmux_set(struct udevice *dev, uint pin_selector, sunxi_pinctrl_get_function_name(dev, func_selector), desc->functions[func_selector].mux); - sunxi_gpio_set_cfgbank(plat->base + bank, pin, - desc->functions[func_selector].mux); + sunxi_gpio_set_cfgbank(plat->base + bank * SUNXI_PINCTRL_BANK_SIZE, + pin, desc->functions[func_selector].mux); return 0; } @@ -102,7 +102,7 @@ static const struct pinconf_param sunxi_pinctrl_pinconf_params[] = { static int sunxi_pinctrl_pinconf_set_pull(struct sunxi_pinctrl_plat *plat, uint bank, uint pin, uint bias) { - struct sunxi_gpio *regs = &plat->base[bank]; + void *regs = plat->base + bank * SUNXI_PINCTRL_BANK_SIZE; sunxi_gpio_set_pull_bank(regs, pin, bias); @@ -112,7 +112,7 @@ static int sunxi_pinctrl_pinconf_set_pull(struct sunxi_pinctrl_plat *plat, static int sunxi_pinctrl_pinconf_set_drive(struct sunxi_pinctrl_plat *plat, uint bank, uint pin, uint drive) { - struct sunxi_gpio *regs = &plat->base[bank]; + void *regs = plat->base + bank * SUNXI_PINCTRL_BANK_SIZE; if (drive < 10 || drive > 40) return -EINVAL; @@ -148,7 +148,7 @@ static int sunxi_pinctrl_get_pin_muxing(struct udevice *dev, uint pin_selector, struct sunxi_pinctrl_plat *plat = dev_get_plat(dev); int bank = pin_selector / SUNXI_GPIOS_PER_BANK; int pin = pin_selector % SUNXI_GPIOS_PER_BANK; - int mux = sunxi_gpio_get_cfgbank(plat->base + bank, pin); + int mux = sunxi_gpio_get_cfgbank(plat->base + bank * SUNXI_PINCTRL_BANK_SIZE, pin); switch (mux) { case SUNXI_GPIO_INPUT: @@ -206,7 +206,7 @@ static int sunxi_pinctrl_bind(struct udevice *dev) if (!gpio_plat) return -ENOMEM; - gpio_plat->regs = plat->base + i; + gpio_plat->regs = plat->base + i * SUNXI_PINCTRL_BANK_SIZE; gpio_plat->bank_name[0] = 'P'; gpio_plat->bank_name[1] = 'A' + desc->first_bank + i; gpio_plat->bank_name[2] = '\0';