diff mbox series

[116/149] global: Migrate CONFIG_SH_ETHER_ALIGNE_SIZE to CFG

Message ID 20221204151420.56851-26-trini@konsulko.com
State Accepted
Commit 24513c3ac85456e8c8256b83ecc44ccaedcee65a
Delegated to: Tom Rini
Headers show
Series None | expand

Commit Message

Tom Rini Dec. 4, 2022, 3:13 p.m. UTC 
Perform a simple rename of CONFIG_SH_ETHER_ALIGNE_SIZE to CFG_SH_ETHER_ALIGNE_SIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
---
 drivers/net/sh_eth.c      |  4 ++--
 drivers/net/sh_eth.h      | 16 ++++++++--------
 include/configs/alt.h     |  2 +-
 include/configs/condor.h  |  2 +-
 include/configs/gose.h    |  2 +-
 include/configs/grpeach.h |  2 +-
 include/configs/koelsch.h |  2 +-
 include/configs/lager.h   |  2 +-
 include/configs/porter.h  |  2 +-
 include/configs/silk.h    |  2 +-
 include/configs/stout.h   |  2 +-
 11 files changed, 19 insertions(+), 19 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 0c584a23b97e..90e47d93aada 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -41,7 +41,7 @@ 
 	!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #define flush_cache_wback(addr, len)    \
 		flush_dcache_range((unsigned long)addr, \
-		(unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
+		(unsigned long)(addr + ALIGN(len, CFG_SH_ETHER_ALIGNE_SIZE)))
 #else
 #define flush_cache_wback(...)
 #endif
@@ -49,7 +49,7 @@ 
 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
 #define invalidate_cache(addr, len)		\
 	{	\
-		unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;	\
+		unsigned long line_size = CFG_SH_ETHER_ALIGNE_SIZE;	\
 		unsigned long start, end;	\
 		\
 		start = (unsigned long)addr;	\
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 520f7f732574..1c07610e1ac7 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -29,8 +29,8 @@ 
 #endif /* defined(CONFIG_SH) */
 
 /* base padding size is 16 */
-#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
-#define CONFIG_SH_ETHER_ALIGNE_SIZE 16
+#ifndef CFG_SH_ETHER_ALIGNE_SIZE
+#define CFG_SH_ETHER_ALIGNE_SIZE 16
 #endif
 
 /* Number of supported ports */
@@ -47,7 +47,7 @@ 
 
 /* The size of the tx descriptor is determined by how much padding is used.
    4, 20, or 52 bytes of padding can be used */
-#define TX_DESC_PADDING	(CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+#define TX_DESC_PADDING	(CFG_SH_ETHER_ALIGNE_SIZE - 12)
 
 /* Tx descriptor. We always use 3 bytes of padding */
 struct tx_desc_s {
@@ -62,9 +62,9 @@  struct tx_desc_s {
 
 /* The size of the rx descriptor is determined by how much padding is used.
    4, 20, or 52 bytes of padding can be used */
-#define RX_DESC_PADDING	(CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+#define RX_DESC_PADDING	(CFG_SH_ETHER_ALIGNE_SIZE - 12)
 /* aligned cache line size */
-#define RX_BUF_ALIGNE_SIZE	(CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
+#define RX_BUF_ALIGNE_SIZE	(CFG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
 
 /* Rx descriptor. We always use 4 bytes of padding */
 struct rx_desc_s {
@@ -388,11 +388,11 @@  enum DMAC_M_BIT {
 #endif
 };
 
-#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
+#if CFG_SH_ETHER_ALIGNE_SIZE == 64
 # define EMDR_DESC EDMR_DL1
-#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
+#elif CFG_SH_ETHER_ALIGNE_SIZE == 32
 # define EMDR_DESC EDMR_DL0
-#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
+#elif CFG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
 # define EMDR_DESC 0
 #endif
 
diff --git a/include/configs/alt.h b/include/configs/alt.h
index 29f4d06b7f83..f06ceed47f0c 100644
--- a/include/configs/alt.h
+++ b/include/configs/alt.h
@@ -26,7 +26,7 @@ 
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
-#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CFG_SH_ETHER_ALIGNE_SIZE	64
 
 /* Board Clock */
 
diff --git a/include/configs/condor.h b/include/configs/condor.h
index 819184996e69..6d7c788163d3 100644
--- a/include/configs/condor.h
+++ b/include/configs/condor.h
@@ -19,7 +19,7 @@ 
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
-#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CFG_SH_ETHER_ALIGNE_SIZE	64
 
 /* Board Clock */
 /* XTAL_CLK : 33.33MHz */
diff --git a/include/configs/gose.h b/include/configs/gose.h
index 45f0ec6f6a0e..93157de470bd 100644
--- a/include/configs/gose.h
+++ b/include/configs/gose.h
@@ -25,7 +25,7 @@ 
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
-#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CFG_SH_ETHER_ALIGNE_SIZE	64
 
 /* Board Clock */
 
diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h
index dd6b22de7bac..5b91e6ff039b 100644
--- a/include/configs/grpeach.h
+++ b/include/configs/grpeach.h
@@ -22,6 +22,6 @@ 
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
-#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CFG_SH_ETHER_ALIGNE_SIZE	64
 
 #endif	/* __GRPEACH_H */
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index 61ff80d2c983..ff02a875013c 100644
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -25,7 +25,7 @@ 
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
-#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CFG_SH_ETHER_ALIGNE_SIZE	64
 
 /* Board Clock */
 
diff --git a/include/configs/lager.h b/include/configs/lager.h
index 777d5b94d1cd..83e8705dfe76 100644
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -26,7 +26,7 @@ 
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
-#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CFG_SH_ETHER_ALIGNE_SIZE	64
 
 /* Board Clock */
 
diff --git a/include/configs/porter.h b/include/configs/porter.h
index 202bd914d506..8f834f2c7eba 100644
--- a/include/configs/porter.h
+++ b/include/configs/porter.h
@@ -27,7 +27,7 @@ 
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
-#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CFG_SH_ETHER_ALIGNE_SIZE	64
 
 /* Board Clock */
 
diff --git a/include/configs/silk.h b/include/configs/silk.h
index 9114a0575828..80fce05b3999 100644
--- a/include/configs/silk.h
+++ b/include/configs/silk.h
@@ -27,7 +27,7 @@ 
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
-#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CFG_SH_ETHER_ALIGNE_SIZE	64
 
 /* Board Clock */
 
diff --git a/include/configs/stout.h b/include/configs/stout.h
index ea5828b950b1..d8f0fb185630 100644
--- a/include/configs/stout.h
+++ b/include/configs/stout.h
@@ -31,7 +31,7 @@ 
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
-#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CFG_SH_ETHER_ALIGNE_SIZE	64
 
 /* Board Clock */