@@ -1297,6 +1297,9 @@ config SYS_NUM_TLBCAMS
Number of TLB CAM entries for Book-E chips. 64 for E500MC,
16 for other E500 SoCs.
+config L2_CACHE
+ bool "Enable L2 cache support"
+
if HETROGENOUS_CLUSTERS
config SYS_MAPLE
@@ -13,6 +13,7 @@ CONFIG_SRIO1=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_USE_UBOOTPATH=y
CONFIG_UBOOTPATH="8548cds/u-boot.bin"
@@ -13,6 +13,7 @@ CONFIG_SRIO1=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_USE_UBOOTPATH=y
CONFIG_UBOOTPATH="8548cds/u-boot.bin"
@@ -13,6 +13,7 @@ CONFIG_SRIO1=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_TARGET_MPC8548CDS_LEGACY=y
CONFIG_USE_UBOOTPATH=y
@@ -16,6 +16,7 @@ CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
@@ -14,6 +14,7 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -16,6 +16,7 @@ CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -16,6 +16,7 @@ CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
@@ -14,6 +14,7 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -16,6 +16,7 @@ CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -16,6 +16,7 @@ CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
@@ -14,6 +14,7 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -16,6 +16,7 @@ CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -16,6 +16,7 @@ CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
@@ -14,6 +14,7 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -16,6 +16,7 @@ CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -16,6 +16,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -14,6 +14,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -16,6 +16,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -10,6 +10,7 @@ CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
@@ -16,6 +16,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -14,6 +14,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -16,6 +16,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -10,6 +10,7 @@ CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
@@ -16,6 +16,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -14,6 +14,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -16,6 +16,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -10,6 +10,7 @@ CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
@@ -16,6 +16,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -14,6 +14,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -16,6 +16,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -10,6 +10,7 @@ CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
@@ -16,6 +16,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -14,6 +14,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -16,6 +16,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -10,6 +10,7 @@ CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
@@ -10,6 +10,7 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_SOCRATES=y
+CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MONITOR_LEN=393216
CONFIG_FIT=y
@@ -17,11 +17,6 @@
#include <linux/stringify.h>
#endif
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-
/*
* Only possible on E500 Version 2 or newer cores.
*/
@@ -95,11 +95,6 @@
#endif
#endif
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-
/* DDR Setup */
#define SPD_EEPROM_ADDRESS 0x52
@@ -109,11 +109,6 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE
-
#define CFG_SYS_CCSRBAR 0xffe00000
#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
@@ -34,11 +34,6 @@
* in the README.mpc85xxads.
*/
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-
#define CFG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
#undef CFG_SYS_DRAM_TEST /* memory test, takes time */
This converts the following to Kconfig: CONFIG_L2_CACHE Signed-off-by: Tom Rini <trini@konsulko.com> --- arch/powerpc/cpu/mpc85xx/Kconfig | 3 +++ configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8548CDS_defconfig | 1 + configs/MPC8548CDS_legacy_defconfig | 1 + configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PA_NAND_defconfig | 1 + configs/P1010RDB-PA_NOR_defconfig | 1 + configs/P1010RDB-PA_SDCARD_defconfig | 1 + configs/P1010RDB-PA_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_NAND_defconfig | 1 + configs/P1010RDB-PB_NOR_defconfig | 1 + configs/P1010RDB-PB_SDCARD_defconfig | 1 + configs/P1010RDB-PB_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_defconfig | 1 + configs/P1020RDB-PC_NAND_defconfig | 1 + configs/P1020RDB-PC_SDCARD_defconfig | 1 + configs/P1020RDB-PC_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_defconfig | 1 + configs/P1020RDB-PD_NAND_defconfig | 1 + configs/P1020RDB-PD_SDCARD_defconfig | 1 + configs/P1020RDB-PD_SPIFLASH_defconfig | 1 + configs/P1020RDB-PD_defconfig | 1 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_36BIT_defconfig | 1 + configs/P2020RDB-PC_NAND_defconfig | 1 + configs/P2020RDB-PC_SDCARD_defconfig | 1 + configs/P2020RDB-PC_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_defconfig | 1 + configs/socrates_defconfig | 1 + include/configs/MPC8548CDS.h | 5 ----- include/configs/P1010RDB.h | 5 ----- include/configs/p1_p2_rdb_pc.h | 5 ----- include/configs/socrates.h | 5 ----- 45 files changed, 43 insertions(+), 20 deletions(-)