@@ -373,12 +373,6 @@ The following options need to be configured:
such as ARM architectural timer initialization.
- Linux Kernel Interface:
- CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only]
-
- When transferring memsize parameter to Linux, some versions
- expect it to be in bytes, others in MB.
- Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
-
CONFIG_OF_LIBFDT
New kernel versions are expecting firmware settings to be
@@ -585,11 +579,6 @@ The following options need to be configured:
Support for generic parallel port TPM devices. Only one device
per system is supported at this time.
- CONFIG_TPM_TIS_BASE_ADDRESS
- Base address where the generic TPM device is mapped
- to. Contemporary x86 systems usually map it at
- 0xfed40000.
-
CONFIG_TPM
Define this to enable the TPM support library which provides
functional interfaces to some TPM commands.
@@ -70,7 +70,6 @@
/* SATA */
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
#ifdef CONFIG_DDR_SPD
-#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
#endif
@@ -30,13 +30,4 @@
/* Needed for SPI NOR booting in SPL */
#define CONFIG_DM_SEQ_ALIAS 1
-/*
- * I2C related stuff
- */
-#ifdef CONFIG_CMD_I2C
-#ifndef CONFIG_SYS_I2C_SOFT
-#define CONFIG_I2C_MVTWSI
-#endif
-#endif
-
#endif /* __MVEBU_CONFIG_H */
@@ -133,7 +133,6 @@
#define CFG_SYS_FM_MURAM_SIZE 0x60000
#ifdef CONFIG_ARCH_B4860
-#define CONFIG_NUM_DSP_CPUS 6
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CFG_SYS_NUM_FM1_DTSEC 6
#define CFG_SYS_NUM_FM1_10GEC 2
@@ -14,7 +14,6 @@
* restricting used physical memory to the first 128MB.
*/
#if XCHAL_HAVE_PTP_MMU
-#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED (128 << 20)
#endif
@@ -140,7 +140,7 @@ void mv_phy_init(char *name)
/* reset the phy */
miiphy_reset(name, devadr);
- printf(PHY_NO" Initialized on %s\n", name);
+ printf("Initialized on %s\n", name);
}
void reset_phy(void)
@@ -37,10 +37,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_MVGBE_PORTS
-# define CONFIG_MVGBE_PORTS {0, 0}
-#endif
-
#define MV_PHY_ADR_REQUEST 0xee
#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
#define MVGBE_PGADR_REG 22
@@ -11,13 +11,6 @@
#ifndef __MVGBE_H__
#define __MVGBE_H__
-/* PHY_BASE_ADR is board specific and can be configured */
-#if defined (CONFIG_PHY_BASE_ADR)
-#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR
-#else
-#define PHY_BASE_ADR 0x08 /* default phy base addr */
-#endif
-
/* Constants */
#define INT_CAUSE_UNMASK_ALL 0x0007ffff
#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
@@ -118,12 +118,7 @@ int dram_init(void)
phys_size_t get_effective_memsize(void)
{
- if (!IS_ENABLED(CONFIG_VERY_BIG_RAM))
- return gd->ram_size;
-
- /* Limit stack to what we can reasonable map */
- return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
- CONFIG_MAX_MEM_MAPPED : gd->ram_size);
+ return gd->ram_size;
}
/**
@@ -195,12 +195,10 @@
* Environment Configuration
*/
-#define CONFIG_NETDEV "eth1"
-
-#define CONFIG_FDTFILE "mpc8379_rdb.dtb"
+#define FDTFILE "mpc8379_rdb.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" CONFIG_NETDEV "\0" \
+ "netdev=eth1\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftp $loadaddr $uboot;" \
"protect off " __stringify(CONFIG_TEXT_BASE) \
@@ -214,7 +212,7 @@
"cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
" $filesize\0" \
"fdtaddr=780000\0" \
- "fdtfile=" CONFIG_FDTFILE "\0" \
+ "fdtfile=" FDTFILE "\0" \
"ramdiskaddr=1000000\0" \
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
"console=ttyS0\0" \
@@ -24,7 +24,6 @@
#ifdef CONFIG_SPIFLASH
#ifdef CONFIG_NXP_ESBC
-#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#else
#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
@@ -12,7 +12,6 @@
#define __CONFIG_H
#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
@@ -46,10 +45,9 @@
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CFG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+#define CFG_SYS_INIT_L3_ADDR CONFIG_TEXT_BASE
#ifdef CONFIG_PHYS_64BIT
-#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
- CONFIG_RAMBOOT_TEXT_BASE)
+#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_TEXT_BASE)
#else
#define CFG_SYS_INIT_L3_ADDR_PHYS CFG_SYS_INIT_L3_ADDR
#endif
@@ -62,7 +60,6 @@
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
@@ -88,7 +85,6 @@
#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
-#define CONFIG_FSL_CPLD
#define CPLD_BASE 0xffdf0000 /* CPLD registers */
#ifdef CONFIG_PHYS_64BIT
#define CPLD_BASE_PHYS 0xfffdf0000ull
@@ -131,7 +127,6 @@
#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
@@ -37,14 +37,5 @@
/* size in bytes reserved for initial data */
#include <asm/arch/config.h>
-/* There is no PHY directly connected so don't ask it for link status */
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */
-#define CONFIG_PHY_BASE_ADR 0x01
-#endif /* CONFIG_CMD_NET */
#endif /* _CONFIG_SBX81LIFKW_H */
@@ -42,14 +42,5 @@
/* size in bytes reserved for initial data */
#include <asm/arch/config.h>
-/* There is no PHY directly connected so don't ask it for link status */
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */
-#define CONFIG_PHY_BASE_ADR 0x01
-#endif /* CONFIG_CMD_NET */
#endif /* _CONFIG_SBX81LIFXCAT_H */
@@ -112,7 +112,6 @@
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#if defined(CONFIG_TARGET_T1024RDB)
@@ -269,7 +268,6 @@
#endif
/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
@@ -86,7 +86,6 @@
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
@@ -247,7 +246,6 @@
#endif
/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
@@ -285,8 +283,6 @@
*/
#define CFG_SYS_I2C_RTC_ADDR 0x68
-/*DVI encoder*/
-#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
#endif
/*
@@ -78,7 +78,6 @@
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
@@ -245,7 +244,6 @@
#endif
/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
@@ -78,7 +78,6 @@
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
@@ -210,7 +209,6 @@
#endif
/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
@@ -16,7 +16,6 @@
#ifdef CONFIG_RAMBOOT_PBL
#ifndef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#else
#define RESET_VECTOR_OFFSET 0x27FFC
@@ -60,7 +59,6 @@
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
@@ -71,7 +69,6 @@
#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
@@ -20,9 +20,6 @@
#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* FLASH */
-#define CONFIG_SPI_FLASH_QUAD
-
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
@@ -49,9 +49,6 @@
*/
#define CFG_SYS_FLASH_BANKS_SIZES {0x4000000}
-/* max number of sectors on one chip */
-#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
-
/* environments */
/* SPI FLASH */
@@ -20,10 +20,6 @@
#define CONFIG_TEGRA_ENABLE_UARTA
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-/* SPI */
-#define CONFIG_TEGRA_SLINK_CTRLS 6
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
@@ -22,9 +22,7 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* FLASH */
-#if !defined(CONFIG_MTD_NOR_FLASH)
-#define CONFIG_SH_QSPI_BASE 0xE6B10000
-#else
+#if defined(CONFIG_MTD_NOR_FLASH)
#define CFG_SYS_FLASH_BASE 0x00000000
#define CFG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
#define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) }
@@ -24,10 +24,6 @@
#define CONFIG_TEGRA_ENABLE_UARTA
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-/* SPI */
-#define CONFIG_TEGRA_SLINK_CTRLS 6
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
@@ -22,9 +22,6 @@
#define CONFIG_TEGRA_ENABLE_UARTD
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-/* SPI */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
@@ -14,10 +14,6 @@
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-/* NAND support */
-
-#define CONFIG_FDTADDR 0x84000000
-
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"fdt_addr_r=0x82000000\0" \
@@ -19,9 +19,6 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
-/* SPI */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
@@ -16,13 +16,6 @@
/* Remove or override few declarations from mv-common.h */
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#endif
-
/*
* Enable GPI0 support
*/
@@ -28,10 +28,4 @@
"initrd=/boot/uInitrd\0" \
"bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0"
-/*
- * Ethernet Driver configuration
- */
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 0
-
#endif /* _CONFIG_DOCKSTAR_H */
@@ -13,7 +13,6 @@
#include <environment/ti/dfu.h>
-#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED 0x80000000
#ifndef CONFIG_QSPI_BOOT
@@ -24,10 +24,4 @@
"x_bootargs=console=ttyS0,115200\0" \
"x_bootargs_root=root=/dev/sda2 rootdelay=10\0"
-/*
- * Ethernet Driver configuration
- */
-#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
-#define CONFIG_PHY_BASE_ADR 0
-
#endif /* _CONFIG_DREAMPLUG_H */
@@ -35,12 +35,4 @@
"ipaddr=192.168.1.5\0" \
"usb0Mode=host\0"
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable one port */
-#define CONFIG_PHY_BASE_ADR 8
-#endif /* CONFIG_CMD_NET */
-
#endif /* _CONFIG_DS109_H */
@@ -144,13 +144,5 @@
#define CFG_SYS_DDRUA 0x05
#define CFG_SYS_PJPAR 0xFF
-/*-----------------------------------------------------------------------
- * I2C
- */
-
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_I2C_RTC_ADDR 0x68
-#endif
-
#endif /* _CONFIG_M5282EVB_H */
/*---------------------------------------------------------------------*/
@@ -8,8 +8,6 @@
#include <configs/x86-common.h>
-#undef CONFIG_TPM_TIS_BASE_ADDRESS
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
"stdout=vidconsole\0" \
"stderr=vidconsole\0"
@@ -35,11 +35,11 @@
#if defined(CONFIG_ENV_IS_IN_MMC)
/* RiOTboard */
-#define CONFIG_FDTFILE "imx6dl-riotboard.dtb"
+#define FDTFILE "imx6dl-riotboard.dtb"
#define CFG_SYS_FSL_USDHC_NUM 3
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
/* MarSBoard */
-#define CONFIG_FDTFILE "imx6q-marsboard.dtb"
+#define FDTFILE "imx6q-marsboard.dtb"
#define CFG_SYS_FSL_USDHC_NUM 2
#endif
@@ -79,7 +79,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
CONSOLE_ENV_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
- "fdtfile=" CONFIG_FDTFILE "\0" \
+ "fdtfile=" FDTFILE "\0" \
"finduuid=part uuid mmc 0:1 uuid\0" \
BOOTENV
@@ -49,7 +49,6 @@
/* Ethernet */
#define CONFIG_PHY_ID 0
-#define CONFIG_MACB_SEARCH_PHY
/* MMC */
#ifdef CONFIG_CMD_MMC
@@ -27,8 +27,6 @@
/* MMC SPL */
#define COPY_BL2_FNPTR_ADDR 0x02020030
-#define CONFIG_RD_LVL
-
#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
@@ -8,8 +8,6 @@
#ifndef __CONFIG_EXYNOS5420_H
#define __CONFIG_EXYNOS5420_H
-#define CONFIG_VAR_SIZE_SPL
-
#define CONFIG_IRAM_TOP 0x02074000
#define CONFIG_PHY_IRAM_BASE 0x02020000
@@ -15,10 +15,6 @@
/* select serial console configuration */
-/* IRAM Layout */
-#define CONFIG_IRAM_BASE 0x02100000
-#define CONFIG_IRAM_SIZE 0x58000
-#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
#define CPU_RELEASE_ADDR secondary_boot_addr
/* select serial console configuration */
@@ -36,10 +36,4 @@
"kernel=/boot/uImage\0" \
"bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\0"
-/*
- * Ethernet Driver configuration
- */
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 0
-
#endif /* _CONFIG_GOFLEXHOME_H */
@@ -30,12 +30,4 @@
"fdt=/boot/guruplug-server-plus.dtb\0" \
"bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
-#define CONFIG_PHY_BASE_ADR 0
-#endif /* CONFIG_CMD_NET */
-
#endif /* _CONFIG_GURUPLUG_H */
@@ -24,14 +24,6 @@
"fdt=/boot/ib62x0.dtb\0" \
"bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
-/*
- * Ethernet driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 0
-#endif /* CONFIG_CMD_NET */
-
/*
* SATA driver configuration
*/
@@ -16,14 +16,4 @@
"kernel=/boot/uImage\0" \
"bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
-/*
- * Ethernet driver configuration
- *
- * This board has PCIe Wifi card, so allow Ethernet to be disabled
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 11
-#endif /* CONFIG_CMD_NET */
-
#endif /* _CONFIG_ICONNECT_H */
@@ -18,11 +18,6 @@
#define CONFIG_TEGRA_ENABLE_UARTD
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-/* Environment in eMMC, at the end of 2nd "boot sector" */
-
-/* SPI */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
@@ -39,6 +39,5 @@
/* Network */
#define CONFIG_KSNET_NETCP_V1_5
#define CONFIG_KSNET_CPSW_NUM_PORTS 9
-#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
#endif /* __CONFIG_K2E_EVM_H */
@@ -53,7 +53,6 @@
/* Network */
#define CONFIG_KSNET_NETCP_V1_5
#define CONFIG_KSNET_CPSW_NUM_PORTS 2
-#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */
#define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS
@@ -39,6 +39,5 @@
/* Network */
#define CONFIG_KSNET_NETCP_V1_5
#define CONFIG_KSNET_CPSW_NUM_PORTS 5
-#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
#endif /* __CONFIG_K2L_EVM_H */
@@ -160,7 +160,6 @@
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
@@ -18,7 +18,6 @@
/* DDR */
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
@@ -14,13 +14,6 @@
* Enable platform initialisation via misc_init_r() function
*/
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#endif
-
/*
* Enable GPI0 support
*/
@@ -48,7 +48,6 @@
* Linux Information
*/
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
-#define CONFIG_SETUP_INITRD_TAG
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootenvfile=uEnv.txt\0" \
"fdtfile=da850-lego-ev3.dtb\0" \
@@ -12,7 +12,6 @@
/* Link Definitions */
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
@@ -31,7 +31,6 @@
/* Link Definitions */
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
@@ -107,7 +107,6 @@
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#endif
#ifdef CONFIG_NAND_BOOT
@@ -82,7 +82,6 @@
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#ifdef CONFIG_NAND_BOOT
#define CFG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
@@ -31,7 +31,6 @@
/* Link Definitions */
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
@@ -45,7 +45,6 @@
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
/* IFC Timing Params */
#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
@@ -123,7 +123,6 @@
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#endif
#ifdef CONFIG_NAND_BOOT
@@ -50,7 +50,6 @@
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
/*
* CPLD
@@ -29,7 +29,6 @@
/* Link Definitions */
#define CFG_SYS_FSL_QSPI_BASE 0x20000000
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
@@ -97,7 +97,6 @@
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 6
@@ -81,7 +81,6 @@
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_BRDCFG4_OFFSET 0x54
@@ -16,7 +16,6 @@
/* Link Definitions */
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
@@ -98,7 +98,6 @@
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define QIXIS_LBMAP_SWITCH 0x06
#define QIXIS_LBMAP_MASK 0x0f
@@ -95,7 +95,6 @@
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define QIXIS_LBMAP_SWITCH 0x06
#define QIXIS_LBMAP_MASK 0x0f
@@ -13,7 +13,6 @@
#define CFG_SYS_FLASH_BASE 0x20000000
/* DDR */
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
@@ -11,8 +11,6 @@
*/
#define CONFIG_MALTA
-#define CONFIG_MEMSIZE_IN_BYTES
-
/*
* CPU Configuration
*/
@@ -10,7 +10,6 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED 0x1c000000
#define CFG_SYS_INIT_SP_OFFSET 0x800000
@@ -15,10 +15,7 @@
/* Environment */
-/* Defines for SPL */
-
-#define CONFIG_SPI_ADDR 0x30000000
-#define CFG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO)
+#define CFG_SYS_UBOOT_BASE (0x30000000 + CONFIG_SPL_PAD_TO)
/* SPL -> Uboot */
@@ -86,9 +86,4 @@
#define CFG_SYS_NAND_BASE 0x60000000
#endif
-/* SPI */
-#ifdef CONFIG_CMD_SPI
-#define CONFIG_SPI_HALF_DUPLEX
-#endif
-
#endif /* __CONFIGS_MXS_H__ */
@@ -39,16 +39,4 @@
"bootargs=console=ttyS0,115200\0" \
"autostart=no\0"
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 8
-#endif /* CONFIG_CMD_NET */
-
-/*
- * EFI partition
- */
-
#endif /* _CONFIG_NAS220_H */
@@ -46,8 +46,4 @@
#endif /* CONFIG_SPL_BUILD */
-/* Ethernet driver configuration */
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 1
-
#endif /* _CONFIG_NSA310S_H */
@@ -18,9 +18,6 @@
#define CONFIG_TEGRA_ENABLE_UARTA
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-/* SPI */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
@@ -33,26 +33,4 @@
"x_bootcmd_usb=usb start\0" \
"x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0"
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-# ifdef CONFIG_BOARD_IS_OPENRD_BASE
-# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-# else
-# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
-# endif
-# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
-# define CONFIG_PHY_BASE_ADR 0x0
-# define PHY_NO "88E1121"
-# else
-# define CONFIG_PHY_BASE_ADR 0x8
-# define PHY_NO "88E1116"
-# endif
-#endif /* CONFIG_CMD_NET */
-
-/*
- * SATA Driver configuration
- */
-
#endif /* _CONFIG_OPENRD_BASE_H */
@@ -38,10 +38,4 @@
"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
"source ${loadaddr}\0"
-/* MIU (Memory Interleaving Unit) */
-#define CONFIG_MIU_2BIT_21_7_INTERLEAVED
-
-#define RESERVE_BLOCK_SIZE (512)
-#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
-
#endif /* __CONFIG_H */
@@ -19,9 +19,6 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
-/* SPI */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* _P2371_0000_H */
@@ -19,9 +19,6 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
-/* SPI */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* _P2371_2180_H */
@@ -19,9 +19,6 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
-/* SPI */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* _P2571_H */
@@ -23,9 +23,6 @@
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
-/* Environment at end of QSPI, in the VER partition */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#define BOARD_EXTRA_ENV_SETTINGS \
"preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \
"load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \
@@ -159,11 +159,6 @@
/* PSRAM */
#define PHYS_PSRAM 0x70000000
#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
-/* Slave EBI1, PSRAM connected */
-#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \
- AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \
- AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \
- AT91_MATRIX_SCFG_SLOT_CYCLE(255))
/* USB */
#define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
@@ -23,10 +23,4 @@
"bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \
"ext2load usb 0:1 0x01100000 /uInitrd\0"
-/*
- * Ethernet Driver configuration
- */
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 0
-
#endif /* _CONFIG_POGO_E02_H */
@@ -69,10 +69,4 @@
BOOTENV
#endif /* CONFIG_SPL_BUILD */
-/*
- * Ethernet Driver configuration
- */
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 0
-
#endif /* _CONFIG_POGO_V4_H */
@@ -21,9 +21,6 @@
#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
-/* FLASH */
-#define CONFIG_SPI_FLASH_QUAD
-
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
@@ -29,7 +29,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void);
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
@@ -28,7 +28,6 @@
#define DRAM_RSV_SIZE 0x08000000
#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
-#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
/* ENV setting */
@@ -10,16 +10,6 @@
#define CONFIG_IRAM_BASE 0xff8c0000
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT)
-#else
-/* BSS setup */
-#endif
-
-/* MMC/SD IP block */
-#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000
-
-/* RAW SD card / eMMC locations. */
-
/* FAT sd card locations. */
#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xf8000000
@@ -21,10 +21,4 @@
"x_bootcmd_usb=usb start\0" \
"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
-/*
- * Ethernet Driver configuration
- */
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 0
-
#endif /* _CONFIG_SHEEVAPLUG_H */
@@ -21,9 +21,6 @@
#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* FLASH */
-#define CONFIG_SPI_FLASH_QUAD
-
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
@@ -12,8 +12,6 @@
#include <configs/exynos5-dt-common.h>
#include <configs/exynos5-common.h>
-#define CONFIG_SMDK5420 /* which is in a SMDK5420 */
-
#define CFG_SYS_SDRAM_BASE 0x20000000
/* DRAM Memory Banks */
@@ -34,9 +34,6 @@
/* FLASH and environment organization */
-#define RESERVE_BLOCK_SIZE (512)
-#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
-
/* Ethernet Controllor Driver */
#ifdef CONFIG_CMD_NET
#define CONFIG_ENV_SROM_BANK 1
@@ -11,15 +11,9 @@
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
/* Ethernet on SoC (EMAC) */
-#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
/* The PHY is autodetected, so no MII PHY address is needed here */
#define PHY_ANEG_TIMEOUT 8000
-/* Enable SPI NOR flash reset, needed for SPI booting */
-#define CONFIG_SPI_N25Q256A_RESET
-
-/* Environment setting for SPI flash */
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
@@ -16,9 +16,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-/* High Level Configuration Options */
-#define CONFIG_SOCRATES 1
-
/*
* Only possible on E500 Version 2 or newer cores.
*/
@@ -55,7 +52,6 @@
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
@@ -25,9 +25,6 @@
/* SCIF */
#define CONFIG_SCIF_A
-/* SPI */
-#define CONFIG_SPI_FLASH_QUAD
-
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
@@ -14,7 +14,6 @@
#define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
-#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */
#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE
#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */
@@ -16,12 +16,6 @@
#define CONFIG_TEGRA_ENABLE_UARTD
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-/* Environment in eMMC, at the end of 2nd "boot sector" */
-
-/* SPI */
-#define CONFIG_TEGRA_SLINK_CTRLS 6
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
@@ -20,9 +20,6 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
-/* SPI */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
@@ -39,9 +39,6 @@
/* USB device */
-/* Ethernet Hardware */
-#define CONFIG_MACB_SEARCH_PHY
-
#ifdef CONFIG_SPI_BOOT
/* bootstrap + u-boot + env + linux in serial flash */
/* Use our own mapping for the VInCo platform */
@@ -10,22 +10,6 @@
#ifndef __CONFIG_X86_COMMON_H
#define __CONFIG_X86_COMMON_H
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/* Generic TPM interfaced through LPC bus */
-#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000
-
-/*-----------------------------------------------------------------------
- * Serial Configuration
- */
-
-/*
- * Miscellaneous configurable options
- */
-
/*-----------------------------------------------------------------------
* CPU Features
*/
@@ -34,9 +34,6 @@
#define CONFIG_FEC_ENET_DEV 0
#define CONFIG_FEC_MXC_PHYADDR 0x0
-#define CONFIG_UBOOT_SECTOR_START 0x2
-#define CONFIG_UBOOT_SECTOR_COUNT 0x3fe
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
@@ -75,8 +72,8 @@
"bootz; " \
"fi;\0" \
"uboot=ccv/u-boot.imx\0" \
- "uboot_start="__stringify(CONFIG_UBOOT_SECTOR_START)"\0" \
- "uboot_size="__stringify(CONFIG_UBOOT_SECTOR_COUNT)"\0" \
+ "uboot_start=0x2\0" \
+ "uboot_size=0x3fe\0" \
"update_uboot=if tftp ${uboot}; then " \
"if itest ${filesize} > 0; then " \
"mmc dev 0 1;" \
This removes the following unreferenced CONFIG symbols: CONFIG_FDTADDR CONFIG_FDTFILE CONFIG_FLASH_SECTOR_SIZE CONFIG_FSL_CPLD CONFIG_HDMI_ENCODER_I2C_ADDR CONFIG_I2C_MVTWSI CONFIG_I2C_RTC_ADDR CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE CONFIG_L1_INIT_RAM CONFIG_MACB_SEARCH_PHY CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MTD_NAND_VERIFY_WRITE CONFIG_MVGBE_PORTS CONFIG_NETDEV CONFIG_NUM_DSP_CPUS CONFIG_PHY_BASE_ADR CONFIG_PHY_INTERFACE_MODE CONFIG_PSRAM_SCFG CONFIG_RAMBOOT_SPIFLASH CONFIG_RAMBOOT_TEXT_BASE CONFIG_RD_LVL CONFIG_ROCKCHIP_SDHCI_MAX_FREQ CONFIG_SETUP_INITRD_TAG CONFIG_SH_QSPI_BASE CONFIG_SMDK5420 CONFIG_SOCRATES CONFIG_SPI_ADDR CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_N25Q256A_RESET CONFIG_TEGRA_SLINK_CTRLS CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_UBOOT_SECTOR_COUNT CONFIG_UBOOT_SECTOR_START CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM And also: BL1_SIZE PHY_NO RESERVE_BLOCK_SIZE Signed-off-by: Tom Rini <trini@konsulko.com> --- README | 11 ----------- arch/arm/include/asm/arch-ls102xa/config.h | 1 - arch/arm/mach-mvebu/include/mach/config.h | 9 --------- arch/powerpc/include/asm/config_mpc85xx.h | 1 - arch/xtensa/include/asm/config.h | 1 - board/Marvell/openrd/openrd.c | 2 +- drivers/net/mvgbe.c | 4 ---- drivers/net/mvgbe.h | 7 ------- drivers/ram/mpc83xx_sdram.c | 7 +------ include/configs/MPC837XERDB.h | 8 +++----- include/configs/P1010RDB.h | 1 - include/configs/P2041RDB.h | 9 ++------- include/configs/SBx81LIFKW.h | 9 --------- include/configs/SBx81LIFXCAT.h | 9 --------- include/configs/T102xRDB.h | 2 -- include/configs/T104xRDB.h | 4 ---- include/configs/T208xQDS.h | 2 -- include/configs/T208xRDB.h | 2 -- include/configs/T4240RDB.h | 3 --- include/configs/alt.h | 3 --- include/configs/ax25-ae350.h | 3 --- include/configs/beaver.h | 4 ---- include/configs/blanche.h | 4 +--- include/configs/cardhu.h | 4 ---- include/configs/cei-tk1-som.h | 3 --- include/configs/colibri_vf.h | 4 ---- include/configs/dalmore.h | 3 --- include/configs/dns325.h | 7 ------- include/configs/dockstar.h | 6 ------ include/configs/dra7xx_evm.h | 1 - include/configs/dreamplug.h | 6 ------ include/configs/ds109.h | 8 -------- include/configs/eb_cpu5282.h | 8 -------- include/configs/efi-x86_app.h | 2 -- include/configs/embestmx6boards.h | 6 +++--- include/configs/ethernut5.h | 1 - include/configs/exynos5-common.h | 2 -- include/configs/exynos5420-common.h | 2 -- include/configs/exynos7420-common.h | 4 ---- include/configs/goflexhome.h | 6 ------ include/configs/guruplug.h | 8 -------- include/configs/ib62x0.h | 8 -------- include/configs/iconnect.h | 10 ---------- include/configs/jetson-tk1.h | 5 ----- include/configs/k2e_evm.h | 1 - include/configs/k2g_evm.h | 1 - include/configs/k2l_evm.h | 1 - include/configs/kmcent2.h | 1 - include/configs/kontron_sl28.h | 1 - include/configs/lacie_kw.h | 7 ------- include/configs/legoev3.h | 1 - include/configs/ls1028a_common.h | 1 - include/configs/ls1043a_common.h | 1 - include/configs/ls1043aqds.h | 1 - include/configs/ls1043ardb.h | 1 - include/configs/ls1046a_common.h | 1 - include/configs/ls1046afrwy.h | 1 - include/configs/ls1046aqds.h | 1 - include/configs/ls1046ardb.h | 1 - include/configs/ls1088a_common.h | 1 - include/configs/ls1088aqds.h | 1 - include/configs/ls1088ardb.h | 1 - include/configs/ls2080a_common.h | 1 - include/configs/ls2080aqds.h | 1 - include/configs/ls2080ardb.h | 1 - include/configs/lx2160a_common.h | 1 - include/configs/malta.h | 2 -- include/configs/mt7621.h | 1 - include/configs/mt7629.h | 5 +---- include/configs/mxs.h | 5 ----- include/configs/nas220.h | 12 ------------ include/configs/nsa310s.h | 4 ---- include/configs/nyan-big.h | 3 --- include/configs/openrd.h | 22 ---------------------- include/configs/origen.h | 6 ------ include/configs/p2371-0000.h | 3 --- include/configs/p2371-2180.h | 3 --- include/configs/p2571.h | 3 --- include/configs/p3450-0000.h | 3 --- include/configs/pm9263.h | 5 ----- include/configs/pogo_e02.h | 6 ------ include/configs/pogo_v4.h | 6 ------ include/configs/porter.h | 3 --- include/configs/qemu-ppce500.h | 1 - include/configs/rcar-gen3-common.h | 1 - include/configs/rk3399_common.h | 10 ---------- include/configs/sheevaplug.h | 6 ------ include/configs/silk.h | 3 --- include/configs/smdk5420.h | 2 -- include/configs/smdkv310.h | 3 --- include/configs/socfpga_sr1500.h | 6 ------ include/configs/socrates.h | 4 ---- include/configs/stout.h | 3 --- include/configs/synquacer.h | 1 - include/configs/tec-ng.h | 6 ------ include/configs/venice2.h | 3 --- include/configs/vinco.h | 3 --- include/configs/x86-common.h | 16 ---------------- include/configs/xpress.h | 7 ++----- 99 files changed, 14 insertions(+), 391 deletions(-)