diff mbox series

[v3,3/5] usb: dwc3: Calculate REFCLKPER based on reference clock

Message ID 20221127143156.18327-3-marex@denx.de
State Accepted
Delegated to: Marek Vasut
Headers show
Series [v3,1/5] usb: dwc3: Cache ref_clk pointer in struct dwc3 | expand

Commit Message

Marek Vasut Nov. 27, 2022, 2:31 p.m. UTC 
From: Sean Anderson <sean.anderson@seco.com>

Instead of using a special property to determine the reference clock
period, use the rate of the reference clock. When we have a legacy
snps,ref-clock-period-ns property and no reference clock, use it
instead. Fractional clocks are not currently supported, and will be
dealt with in the next commit.

[ marek: Ported from Linux kernel commit
         5114c3ee24875 ("usb: dwc3: Calculate REFCLKPER based on reference clock") ]

Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux
---
Cc: Angus Ainslie <angus@akkea.ca>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Sean Anderson <sean.anderson@seco.com>
Cc: Stefano Babic <sbabic@denx.de>
---
V2: No change
V3: Include clk.h
---
 drivers/usb/dwc3/core.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 300450100c9..ed5d0d16f78 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -14,6 +14,7 @@ 
  */
 
 #include <common.h>
+#include <clk.h>
 #include <cpu_func.h>
 #include <malloc.h>
 #include <dwc3-uboot.h>
@@ -126,14 +127,24 @@  static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
  */
 static void dwc3_ref_clk_period(struct dwc3 *dwc)
 {
+	unsigned long period;
+	unsigned long rate;
 	u32 reg;
 
-	if (dwc->ref_clk_per == 0)
+	if (dwc->ref_clk) {
+		rate = clk_get_rate(dwc->ref_clk);
+		if (!rate)
+			return;
+		period = NSEC_PER_SEC / rate;
+	} else if (dwc->ref_clk_per) {
+		period = dwc->ref_clk_per;
+	} else {
 		return;
+	}
 
 	reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
 	reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
-	reg |=  FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, dwc->ref_clk_per);
+	reg |=  FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
 	dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
 }