| Message ID | 20221121091528.1351-1-JJLIU0@nuvoton.com |
|---|---|
| State | Accepted |
| Commit | 07f5399f04781568cd8df1cc97c9325d47566289 |
| Delegated to: | Sean Anderson |
| Headers | show |
| Series | [v1] clk: nuvoton: fix bug for calculate pll clock | expand |
On 11/21/22 04:15, Jim Liu wrote: > Fix bug for npcm7xx bmc calculate pll clock. > PLLCON1 need to divide by 2. > > Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> > --- > drivers/clk/nuvoton/clk_npcm7xx.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/nuvoton/clk_npcm7xx.c b/drivers/clk/nuvoton/clk_npcm7xx.c > index a12aaa2f4c..b23dd37af6 100644 > --- a/drivers/clk/nuvoton/clk_npcm7xx.c > +++ b/drivers/clk/nuvoton/clk_npcm7xx.c > @@ -25,7 +25,7 @@ static const struct parent_data apb_parent[] = {{NPCM7XX_CLK_AHB, 0}}; > > static struct npcm_clk_pll npcm7xx_clk_plls[] = { > {NPCM7XX_CLK_PLL0, NPCM7XX_CLK_REFCLK, PLLCON0, 0}, > - {NPCM7XX_CLK_PLL1, NPCM7XX_CLK_REFCLK, PLLCON1, 0}, > + {NPCM7XX_CLK_PLL1, NPCM7XX_CLK_REFCLK, PLLCON1, POST_DIV2}, > {NPCM7XX_CLK_PLL2, NPCM7XX_CLK_REFCLK, PLLCON2, 0}, > {NPCM7XX_CLK_PLL2DIV2, NPCM7XX_CLK_REFCLK, PLLCON2, POST_DIV2} > }; Acked-by: Sean Anderson <seanga2@gmail.com>
On Mon, 21 Nov 2022 17:15:28 +0800, Jim Liu wrote: > Fix bug for npcm7xx bmc calculate pll clock. > PLLCON1 need to divide by 2. > > Applied, thanks! [1/1] clk: nuvoton: fix bug for calculate pll clock commit: af7237596290f8278b1c10f9949020cc6bc47acf Best regards,
diff --git a/drivers/clk/nuvoton/clk_npcm7xx.c b/drivers/clk/nuvoton/clk_npcm7xx.c index a12aaa2f4c..b23dd37af6 100644 --- a/drivers/clk/nuvoton/clk_npcm7xx.c +++ b/drivers/clk/nuvoton/clk_npcm7xx.c @@ -25,7 +25,7 @@ static const struct parent_data apb_parent[] = {{NPCM7XX_CLK_AHB, 0}}; static struct npcm_clk_pll npcm7xx_clk_plls[] = { {NPCM7XX_CLK_PLL0, NPCM7XX_CLK_REFCLK, PLLCON0, 0}, - {NPCM7XX_CLK_PLL1, NPCM7XX_CLK_REFCLK, PLLCON1, 0}, + {NPCM7XX_CLK_PLL1, NPCM7XX_CLK_REFCLK, PLLCON1, POST_DIV2}, {NPCM7XX_CLK_PLL2, NPCM7XX_CLK_REFCLK, PLLCON2, 0}, {NPCM7XX_CLK_PLL2DIV2, NPCM7XX_CLK_REFCLK, PLLCON2, POST_DIV2} };
Fix bug for npcm7xx bmc calculate pll clock. PLLCON1 need to divide by 2. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> --- drivers/clk/nuvoton/clk_npcm7xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)