From patchwork Sun Nov 20 14:08:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rini X-Patchwork-Id: 1706942 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=konsulko.com header.i=@konsulko.com header.a=rsa-sha256 header.s=google header.b=cXBWUSYb; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NFXy81mBgz23mR for ; Mon, 21 Nov 2022 01:31:12 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 513048548B; Sun, 20 Nov 2022 15:22:18 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=konsulko.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=konsulko.com header.i=@konsulko.com header.b="cXBWUSYb"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 86AF08070C; Sun, 20 Nov 2022 15:12:17 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qk1-x736.google.com (mail-qk1-x736.google.com [IPv6:2607:f8b0:4864:20::736]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D806E853B6 for ; Sun, 20 Nov 2022 15:09:45 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=konsulko.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=trini@konsulko.com Received: by mail-qk1-x736.google.com with SMTP id k2so6518626qkk.7 for ; Sun, 20 Nov 2022 06:09:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=konsulko.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0jloXpyJvAtnFrOVLgzYIc3+cJEG4P+8iLY68OGLggk=; b=cXBWUSYbGT//cHPiYtnLhXwegsiV1ZlO1en+ffFjVBGR94Shugnem/y3hjf13ZmUMG TIHlCXDKPv97m/FIgAs9qciDh13A0PcMAkddKvE61ZPiUNosPecKWCjemux49syENM+G lutgWRZGgleqmBXdrLMOvdAUsYEZlu8L64u9E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0jloXpyJvAtnFrOVLgzYIc3+cJEG4P+8iLY68OGLggk=; b=aO5kh2faJYWUgslWadZgsT3N8eLLMXYiegWLTJUSt6SdB9wFJ2zX2yUaSO4s2RTr3h xIDKW+5LrgeEjZiV0T/ehSHTVRAemWkwKADSGatCTkNsmA3tbq/QQahTsCXFVav4VgIP HJBUl9CJGbg72Zv6FwM13yatHzB+UkUYiAY34LEig+2ORx0cOLDrz453nOSya7rU1+2K Ykg3/3EjajQjS8Gex/8W0t4dvtmCLk8xGllVGyZvEWUfOC2KqoEY6PoHA4IS0brzv9JL mnxHBlzY0jsSzIBqtyAU4eITFKRKlwQAelk3vHQQPoUhZDy+YFo6BW6ARLS5b3uR08Nt pF4w== X-Gm-Message-State: ANoB5plY0Ptw2BqtS+HFqbQzOkh7s53k1twTRUZftjPQw/Lax0zlj9W+ JVnKjQjZTW2iqOSO4G+RXgVis7DhGf9jTQ== X-Google-Smtp-Source: AA0mqf49B1tXie5G3I+wqSUROuXqpWrWnzG/8JN+QxH1KiqI8xKADi/dwk4O8AbYmuM5mbizQ1P3zQ== X-Received: by 2002:a05:620a:16b1:b0:6fa:34ba:ec48 with SMTP id s17-20020a05620a16b100b006fa34baec48mr12720856qkj.321.1668953355534; Sun, 20 Nov 2022 06:09:15 -0800 (PST) Received: from bill-the-cat.lan (2603-6081-7b00-6400-29a0-035f-b06a-235e.res6.spectrum.com. [2603:6081:7b00:6400:29a0:35f:b06a:235e]) by smtp.gmail.com with ESMTPSA id bk23-20020a05620a1a1700b006ce580c2663sm6387502qkb.35.2022.11.20.06.09.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Nov 2022 06:09:15 -0800 (PST) From: Tom Rini To: u-boot@lists.denx.de Subject: [PoC 179/241] global: Migrate CONFIG_SH_ETHER_ALIGNE_SIZE to CFG Date: Sun, 20 Nov 2022 09:08:09 -0500 Message-Id: <20221120140829.3057894-70-trini@konsulko.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221120140829.3057894-1-trini@konsulko.com> References: <20221120135520.3057773-4-trini@konsulko.com> <20221120140829.3057894-1-trini@konsulko.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Signed-off-by: Tom Rini --- drivers/net/sh_eth.c | 4 ++-- drivers/net/sh_eth.h | 16 ++++++++-------- include/configs/alt.h | 2 +- include/configs/condor.h | 2 +- include/configs/gose.h | 2 +- include/configs/grpeach.h | 2 +- include/configs/koelsch.h | 2 +- include/configs/lager.h | 2 +- include/configs/porter.h | 2 +- include/configs/silk.h | 2 +- include/configs/stout.h | 2 +- scripts/config_whitelist.txt | 2 +- 12 files changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 1de3ff8add2c..0f91ad4128cd 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -43,7 +43,7 @@ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #define flush_cache_wback(addr, len) \ flush_dcache_range((unsigned long)addr, \ - (unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE))) + (unsigned long)(addr + ALIGN(len, CFG_SH_ETHER_ALIGNE_SIZE))) #else #define flush_cache_wback(...) #endif @@ -51,7 +51,7 @@ #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) #define invalidate_cache(addr, len) \ { \ - unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \ + unsigned long line_size = CFG_SH_ETHER_ALIGNE_SIZE; \ unsigned long start, end; \ \ start = (unsigned long)addr; \ diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 520f7f732574..1c07610e1ac7 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -29,8 +29,8 @@ #endif /* defined(CONFIG_SH) */ /* base padding size is 16 */ -#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 16 +#ifndef CFG_SH_ETHER_ALIGNE_SIZE +#define CFG_SH_ETHER_ALIGNE_SIZE 16 #endif /* Number of supported ports */ @@ -47,7 +47,7 @@ /* The size of the tx descriptor is determined by how much padding is used. 4, 20, or 52 bytes of padding can be used */ -#define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) +#define TX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12) /* Tx descriptor. We always use 3 bytes of padding */ struct tx_desc_s { @@ -62,9 +62,9 @@ struct tx_desc_s { /* The size of the rx descriptor is determined by how much padding is used. 4, 20, or 52 bytes of padding can be used */ -#define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) +#define RX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12) /* aligned cache line size */ -#define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32) +#define RX_BUF_ALIGNE_SIZE (CFG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32) /* Rx descriptor. We always use 4 bytes of padding */ struct rx_desc_s { @@ -388,11 +388,11 @@ enum DMAC_M_BIT { #endif }; -#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64 +#if CFG_SH_ETHER_ALIGNE_SIZE == 64 # define EMDR_DESC EDMR_DL1 -#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32 +#elif CFG_SH_ETHER_ALIGNE_SIZE == 32 # define EMDR_DESC EDMR_DL0 -#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */ +#elif CFG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */ # define EMDR_DESC 0 #endif diff --git a/include/configs/alt.h b/include/configs/alt.h index 6d530f6d24bc..846e755f1b62 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -29,7 +29,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/condor.h b/include/configs/condor.h index 819184996e69..6d7c788163d3 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -19,7 +19,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ /* XTAL_CLK : 33.33MHz */ diff --git a/include/configs/gose.h b/include/configs/gose.h index 45f0ec6f6a0e..93157de470bd 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -25,7 +25,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index dd6b22de7bac..5b91e6ff039b 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -22,6 +22,6 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 #endif /* __GRPEACH_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 61ff80d2c983..ff02a875013c 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -25,7 +25,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/lager.h b/include/configs/lager.h index 777d5b94d1cd..83e8705dfe76 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -26,7 +26,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/porter.h b/include/configs/porter.h index 969e175883bb..ec70c76f46b0 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -30,7 +30,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/silk.h b/include/configs/silk.h index 025d56671122..4da7e7141336 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -30,7 +30,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/stout.h b/include/configs/stout.h index be9013bcf93d..a071d1425bb3 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -34,7 +34,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 6ffe0779b47d..0c8b3c62f23b 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -188,7 +188,7 @@ CFG_SERIAL_BOOT CFG_SERVERIP CFG_SETUP_INITRD_TAG CFG_SET_DFU_ALT_BUF_LEN -CONFIG_SH_ETHER_ALIGNE_SIZE +CFG_SH_ETHER_ALIGNE_SIZE CONFIG_SH_ETHER_CACHE_INVALIDATE CONFIG_SH_ETHER_CACHE_WRITEBACK CONFIG_SH_ETHER_PHY_ADDR