From patchwork Sun Nov 13 14:57:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1703243 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=B0m36esO; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N9Ftb0ng0z23n0 for ; Mon, 14 Nov 2022 01:58:15 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id ED00685177; Sun, 13 Nov 2022 15:57:36 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="B0m36esO"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 564BF85173; Sun, 13 Nov 2022 15:57:26 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 48D2085177 for ; Sun, 13 Nov 2022 15:57:17 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668351437; x=1699887437; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mHCnKo3Wa1jdnBTm5x2JysfztWy4XnfF0qGPX2ia7Nc=; b=B0m36esOYIzOiciziFmR9Uwtc6bwc0RURTCQp5zeJER92npVnPb9KHwQ 2Et5YurjTXb52RTHjWxxk04Mauz0WIzFvx7CLEZG1qMxRT3rUrI9xRpVZ 6sUxh4Z5ctt2xNJljxy7A9uTTxny8aXdFRs6Knuv2rEcxJr/7g/4+vAGV 0c6xwRFyPt9z1j7N7pJKhagOUWIXPqrPdWSdeWpu8/y1LjFHezP1s9ApI izovULYAE4ZNTYq2JKXLayXHMi7kv1gBfnlpHCdKOKB8gIGl2jKHJs/uo miqOX+XchaXl+mB/17A3VMB1AJAXxy3GABtzy76/799QQfJWj1lba4oLV g==; X-IronPort-AV: E=McAfee;i="6500,9779,10529"; a="292215257" X-IronPort-AV: E=Sophos;i="5.96,161,1665471600"; d="scan'208";a="292215257" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2022 06:57:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10529"; a="967287429" X-IronPort-AV: E=Sophos;i="5.96,161,1665471600"; d="scan'208";a="967287429" Received: from pglmail07.png.intel.com ([10.221.193.207]) by fmsmga005.fm.intel.com with ESMTP; 13 Nov 2022 06:57:11 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id BBF47355B; Sun, 13 Nov 2022 22:57:10 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id BB7C4E0094D; Sun, 13 Nov 2022 22:57:10 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Ley Foon Tan Subject: [PATCH 5/5] arm: socfpga: soc64: Avoid hang in bridge reset Date: Sun, 13 Nov 2022 22:57:06 +0800 Message-Id: <20221113145706.5002-5-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20221113145706.5002-1-jit.loon.lim@intel.com> References: <20221113145706.5002-1-jit.loon.lim@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Ley Foon Tan HSD #1508586908-6: Software shouldn't hang the system if the HPS bridge reset is failed. Change hang() to error message. Signed-off-by: Ley Foon Tan Signed-off-by: Jit Loon Lim --- .../include/mach/base_addr_soc64.h | 1 + arch/arm/mach-socfpga/include/mach/timer.h | 31 +++++++++++++++++++ arch/arm/mach-socfpga/reset_manager_s10.c | 12 +++++-- 3 files changed, 41 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 3f899fcfa3..c0de59f279 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -16,6 +16,7 @@ #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 #endif +#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0xf8024000 #define SOCFPGA_SMMU_ADDRESS 0xfa000000 #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 diff --git a/arch/arm/mach-socfpga/include/mach/timer.h b/arch/arm/mach-socfpga/include/mach/timer.h index 82596e412e..be56b4968f 100644 --- a/arch/arm/mach-socfpga/include/mach/timer.h +++ b/arch/arm/mach-socfpga/include/mach/timer.h @@ -6,6 +6,9 @@ #ifndef _SOCFPGA_TIMER_H_ #define _SOCFPGA_TIMER_H_ +#include +#include + struct socfpga_timer { u32 load_val; u32 curr_val; @@ -14,4 +17,32 @@ struct socfpga_timer { u32 int_stat; }; +static __always_inline u64 __socfpga_get_time_stamp(void) +{ + u64 cntpct; + + isb(); + asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct)); + return cntpct; +} + +static __always_inline u64 __socfpga_usec_to_tick(u64 usec) +{ + u64 tick = usec; + u64 cntfrq; + + asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq)); + tick *= cntfrq; + do_div(tick, 1000000); + return tick; +} + +static __always_inline void __socfpga_udelay(u64 usec) +{ + u64 tmp = __socfpga_get_time_stamp() + __socfpga_usec_to_tick(usec); + + while (__socfpga_get_time_stamp() < tmp + 1) + ; +} + #endif diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index 690cfb2b20..0274c4dbdb 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -8,13 +8,15 @@ #include #include #include +#include #include #include #include +#include #include +#include #include #include - DECLARE_GLOBAL_DATA_PTR; /* F2S manager registers */ @@ -223,9 +225,13 @@ void socfpga_bridges_reset(int enable) { if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) { u64 arg = enable; + int ret; - if (invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0)) - hang(); + ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, + 0); + if (ret) + printf("Failed to %s the HPS bridges, error %d\n", + enable ? "enable" : "disable", ret); } else { socfpga_s2f_bridges_reset(enable); socfpga_f2s_bridges_reset(enable);