diff mbox series

[2/5] arm: socfpga: soc64: Update reset manager registers

Message ID 20221113145706.5002-2-jit.loon.lim@intel.com
State Needs Review / ACK, archived
Delegated to: Marek Vasut
Headers show
Series [1/5] arm: socfpga: Add F2SDRAM_MANAGER base address | expand

Commit Message

Jit Loon Lim Nov. 13, 2022, 2:57 p.m. UTC 
From: Ley Foon Tan <ley.foon.tan@intel.com>

HSD #1508586908-2: Add reset manager registers, preparation for f2s bridge reset support.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
 arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h | 1 -
 1 file changed, 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
index ca5739c30c..9589b61749 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
@@ -29,7 +29,6 @@  void socfpga_bridges_reset(int enable);
 #define RSTMGR_BRGMODRST_F2SDRAM1_MASK	BIT(4)
 #define RSTMGR_BRGMODRST_F2SDRAM2_MASK	BIT(5)
 #define RSTMGR_BRGMODRST_DDRSCH_MASK	BIT(6)
-
 #define BRGMODRST_SOC2FPGA_BRIDGES	(RSTMGR_BRGMODRST_SOC2FPGA_MASK | \
 					 RSTMGR_BRGMODRST_LWSOC2FPGA_MASK)
 #define BRGMODRST_FPGA2SOC_BRIDGES	(RSTMGR_BRGMODRST_FPGA2SOC_MASK | \