| Message ID | 20221025075848.110754-6-conor.dooley@microchip.com |
|---|---|
| State | Accepted |
| Commit | 4e405c68fbf53e52fdb36631caa090c081c59bd0 |
| Delegated to: | Andes |
| Headers | show |
| Series | clk: microchip: mpfs: incremental fixes | expand |
On Tue, Oct 25, 2022 at 08:58:48AM +0100, Conor Dooley wrote: > Sync the critical clocks in the U-Boot driver with those marked as > critical in Linux. The Linux driver has an explanation of why each clock > is considered to be critical, so import that too. > > Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > drivers/clk/microchip/mpfs_clk_periph.c | 28 ++++++++++++++++++------- > 1 file changed, 21 insertions(+), 7 deletions(-) Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> On Tue, 2022-10-25 at 08:58 +0100, Conor Dooley wrote: > Sync the critical clocks in the U-Boot driver with those marked as > critical in Linux. The Linux driver has an explanation of why each > clock > is considered to be critical, so import that too. > > Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > drivers/clk/microchip/mpfs_clk_periph.c | 28 ++++++++++++++++++----- > -- > 1 file changed, 21 insertions(+), 7 deletions(-) > > diff --git a/drivers/clk/microchip/mpfs_clk_periph.c > b/drivers/clk/microchip/mpfs_clk_periph.c > index e23eb552c3..ddeccb9145 100644 > --- a/drivers/clk/microchip/mpfs_clk_periph.c > +++ b/drivers/clk/microchip/mpfs_clk_periph.c > @@ -114,13 +114,27 @@ static ulong mpfs_periph_clk_recalc_rate(struct > clk *hw) > .periph.flags = _flags, \ > } > > +/* > + * Critical clocks: > + * - CLK_ENVM: reserved by hart software services (hss) superloop > monitor/m mode interrupt > + * trap handler > + * - CLK_MMUART0: reserved by the hss > + * - CLK_DDRC: provides clock to the ddr subsystem > + * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running > as the rtc will stop > + * if the AHB interface clock is disabled > + * - CLK_FICx: these provide the processor side clocks to the "FIC" > (Fabric InterConnect) > + * clock domain crossers which provide the interface to the FPGA > fabric. Disabling them > + * causes the FPGA fabric to go into reset. > + * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the > Athena TeraFire. > + */ > + > static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { > CLK_PERIPH(CLK_ENVM, "clk_periph_envm", CLK_AHB, 0, > CLK_IS_CRITICAL), > CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", CLK_AHB, 1, 0), > CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", CLK_AHB, 2, 0), > CLK_PERIPH(CLK_MMC, "clk_periph_mmc", CLK_AHB, 3, 0), > CLK_PERIPH(CLK_TIMER, "clk_periph_timer", CLK_RTCREF, 4, 0), > - CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", CLK_AHB, 5, 0), > + CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", CLK_AHB, 5, > CLK_IS_CRITICAL), > CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", CLK_AHB, 6, 0), > CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", CLK_AHB, 7, 0), > CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", CLK_AHB, 8, 0), > @@ -132,17 +146,17 @@ static struct mpfs_periph_hw_clock > mpfs_periph_clks[] = { > CLK_PERIPH(CLK_CAN0, "clk_periph_can0", CLK_AHB, 14, 0), > CLK_PERIPH(CLK_CAN1, "clk_periph_can1", CLK_AHB, 15, 0), > CLK_PERIPH(CLK_USB, "clk_periph_usb", CLK_AHB, 16, 0), > - CLK_PERIPH(CLK_RTC, "clk_periph_rtc", CLK_AHB, 18, 0), > + CLK_PERIPH(CLK_RTC, "clk_periph_rtc", CLK_AHB, 18, > CLK_IS_CRITICAL), > CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", CLK_AHB, 19, 0), > CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", CLK_AHB, 20, 0), > CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", CLK_AHB, 21, 0), > CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", CLK_AHB, 22, 0), > CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", CLK_AHB, 23, > CLK_IS_CRITICAL), > - CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", CLK_AXI, 24, 0), > - CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", CLK_AXI, 25, 0), > - CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", CLK_AXI, 26, 0), > - CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", CLK_AXI, 27, 0), > - CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", CLK_AXI, 28, 0), > + CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", CLK_AXI, 24, > CLK_IS_CRITICAL), > + CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", CLK_AXI, 25, > CLK_IS_CRITICAL), > + CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", CLK_AXI, 26, > CLK_IS_CRITICAL), > + CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", CLK_AXI, 27, > CLK_IS_CRITICAL), > + CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", CLK_AXI, 28, > CLK_IS_CRITICAL), > CLK_PERIPH(CLK_CFM, "clk_periph_cfm", CLK_AHB, 29, 0), > }; > Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
diff --git a/drivers/clk/microchip/mpfs_clk_periph.c b/drivers/clk/microchip/mpfs_clk_periph.c index e23eb552c3..ddeccb9145 100644 --- a/drivers/clk/microchip/mpfs_clk_periph.c +++ b/drivers/clk/microchip/mpfs_clk_periph.c @@ -114,13 +114,27 @@ static ulong mpfs_periph_clk_recalc_rate(struct clk *hw) .periph.flags = _flags, \ } +/* + * Critical clocks: + * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt + * trap handler + * - CLK_MMUART0: reserved by the hss + * - CLK_DDRC: provides clock to the ddr subsystem + * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop + * if the AHB interface clock is disabled + * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect) + * clock domain crossers which provide the interface to the FPGA fabric. Disabling them + * causes the FPGA fabric to go into reset. + * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire. + */ + static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { CLK_PERIPH(CLK_ENVM, "clk_periph_envm", CLK_AHB, 0, CLK_IS_CRITICAL), CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", CLK_AHB, 1, 0), CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", CLK_AHB, 2, 0), CLK_PERIPH(CLK_MMC, "clk_periph_mmc", CLK_AHB, 3, 0), CLK_PERIPH(CLK_TIMER, "clk_periph_timer", CLK_RTCREF, 4, 0), - CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", CLK_AHB, 5, 0), + CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", CLK_AHB, 5, CLK_IS_CRITICAL), CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", CLK_AHB, 6, 0), CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", CLK_AHB, 7, 0), CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", CLK_AHB, 8, 0), @@ -132,17 +146,17 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { CLK_PERIPH(CLK_CAN0, "clk_periph_can0", CLK_AHB, 14, 0), CLK_PERIPH(CLK_CAN1, "clk_periph_can1", CLK_AHB, 15, 0), CLK_PERIPH(CLK_USB, "clk_periph_usb", CLK_AHB, 16, 0), - CLK_PERIPH(CLK_RTC, "clk_periph_rtc", CLK_AHB, 18, 0), + CLK_PERIPH(CLK_RTC, "clk_periph_rtc", CLK_AHB, 18, CLK_IS_CRITICAL), CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", CLK_AHB, 19, 0), CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", CLK_AHB, 20, 0), CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", CLK_AHB, 21, 0), CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", CLK_AHB, 22, 0), CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", CLK_AHB, 23, CLK_IS_CRITICAL), - CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", CLK_AXI, 24, 0), - CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", CLK_AXI, 25, 0), - CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", CLK_AXI, 26, 0), - CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", CLK_AXI, 27, 0), - CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", CLK_AXI, 28, 0), + CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", CLK_AXI, 24, CLK_IS_CRITICAL), + CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", CLK_AXI, 25, CLK_IS_CRITICAL), + CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", CLK_AXI, 26, CLK_IS_CRITICAL), + CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", CLK_AXI, 27, CLK_IS_CRITICAL), + CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", CLK_AXI, 28, CLK_IS_CRITICAL), CLK_PERIPH(CLK_CFM, "clk_periph_cfm", CLK_AHB, 29, 0), };
Sync the critical clocks in the U-Boot driver with those marked as critical in Linux. The Linux driver has an explanation of why each clock is considered to be critical, so import that too. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- drivers/clk/microchip/mpfs_clk_periph.c | 28 ++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-)