diff mbox series

[v4,3/3] riscv: Fix build against binutils 2.38

Message ID 20221003160754.6991-4-heinrich.schuchardt@canonical.com
State Accepted
Delegated to: Tom Rini
Headers show
Series riscv: Fix build against binutils 2.38 | expand

Commit Message

Heinrich Schuchardt Oct. 3, 2022, 4:07 p.m. UTC 
From: Alexandre Ghiti <alexandre.ghiti@canonical.com>

The following description is copied from the equivalent patch for the
Linux Kernel proposed by Aurelien Jarno:

>From version 2.38, binutils default to ISA spec version 20191213. This
means that the csr read/write (csrr*/csrw*) instructions and fence.i
instruction has separated from the `I` extension, become two standalone
extensions: Zicsr and Zifencei. As the kernel uses those instruction,
this causes the following build failure:

arch/riscv/cpu/mtrap.S: Assembler messages:
arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'

Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Christian Stewart <christian@paral.in>
Reviewed-by: Rick Chen <rick@andestech.com>
---
v4:
	no change
v3:
	no change
---
 arch/riscv/Makefile | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

Comments

Tom Rini Oct. 7, 2022, 3:50 p.m. UTC | #1 
On Mon, Oct 03, 2022 at 06:07:54PM +0200, Heinrich Schuchardt wrote:

> From: Alexandre Ghiti <alexandre.ghiti@canonical.com>
> 
> The following description is copied from the equivalent patch for the
> Linux Kernel proposed by Aurelien Jarno:
> 
> >From version 2.38, binutils default to ISA spec version 20191213. This
> means that the csr read/write (csrr*/csrw*) instructions and fence.i
> instruction has separated from the `I` extension, become two standalone
> extensions: Zicsr and Zifencei. As the kernel uses those instruction,
> this causes the following build failure:
> 
> arch/riscv/cpu/mtrap.S: Assembler messages:
> arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
> arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
> arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
> arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
> 
> Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> Tested-by: Heiko Stuebner <heiko@sntech.de>
> Tested-by: Christian Stewart <christian@paral.in>
> Reviewed-by: Rick Chen <rick@andestech.com>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 0b80eb8d86..53d1194ffb 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -24,7 +24,16 @@  ifeq ($(CONFIG_CMODEL_MEDANY),y)
 	CMODEL = medany
 endif
 
-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
+RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
+
+# Newer binutils versions default to ISA spec version 20191213 which moves some
+# instructions from the I extension to the Zicsr and Zifencei extensions.
+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
+ifeq ($(toolchain-need-zicsr-zifencei),y)
+	RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
+endif
+
+ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
 	     -mcmodel=$(CMODEL)
 
 PLATFORM_CPPFLAGS	+= $(ARCH_FLAGS)