From patchwork Mon Sep 19 01:06:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chong, Teik Heng" X-Patchwork-Id: 1679131 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Yunm/6fT; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MW62f2mqQz1yp7 for ; Mon, 19 Sep 2022 11:06:48 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4598184A92; Mon, 19 Sep 2022 03:06:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Yunm/6fT"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4539184BE8; Mon, 19 Sep 2022 03:06:38 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id CA1E6849AA for ; Mon, 19 Sep 2022 03:06:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=teik.heng.chong@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663549595; x=1695085595; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=a15/UXP81N1GDuyuCY6e/rC7D/koe12imsmIbSfBzsw=; b=Yunm/6fTUF3SjqequBshJcVCgg0Kd8R7MikNBAfPlDK2CF4bA+eL4FaV yHRbxp/3bGXbPk4rqF2lkkmRuu/+/87sEtBgBL1Zf1OFAnO+lAVfbs+V0 7mcY0wmybn+aBJdHDTNx4mjIPGCsNtlB1qAjvYq82geQkvjmcBBAWtl7H Du7e7rNKahvBdaQeglKndmIkjWTejvdXWUOQyigOGl24cPGpyQKWJEHLV dNmNKRVdU2/GX+HrL5USCp2LGvrT7gw7l85xZCRO3mwY/dHAEkEWSq9mU kK0Y3FjzXpmE6I+NMEsN37z0jSbHzpCB4Kmf29ZbGlXzzFiTUpukpVKbq Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10474"; a="296870993" X-IronPort-AV: E=Sophos;i="5.93,325,1654585200"; d="scan'208";a="296870993" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2022 18:06:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,325,1654585200"; d="scan'208";a="722092436" Received: from pgli4336.png.intel.com ([10.221.172.41]) by fmsmga002.fm.intel.com with ESMTP; 18 Sep 2022 18:06:29 -0700 From: teik.heng.chong@intel.com To: u-boot@lists.denx.de Cc: Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang Subject: [PATCH] arm: socfpga: Remove confusing timer related words from watchdog reset Date: Mon, 19 Sep 2022 09:06:26 +0800 Message-Id: <20220919010626.9473-1-teik.heng.chong@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee It's confusing to have timer related words along with watchdog reset dessert function, because the function is only release watchdog from reset, so it has no related to any timer setting. Signed-off-by: Tien Fong Chee Signed-off-by: Teik Heng Chong --- arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h | 2 +- arch/arm/mach-socfpga/reset_manager_arria10.c | 4 ++-- arch/arm/mach-socfpga/spl_a10.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h index 26faa628a0..9aacf3e2c6 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h @@ -12,7 +12,7 @@ void socfpga_watchdog_disable(void); void socfpga_reset_deassert_noc_ddr_scheduler(void); int socfpga_reset_deassert_bridges_handoff(void); -void socfpga_reset_deassert_osc1wd0(void); +void socfpga_reset_deassert_wd0(void); int socfpga_bridges_reset(void); #define RSTMGR_A10_STATUS 0x00 diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c index 27c0308011..13a5cf314b 100644 --- a/arch/arm/mach-socfpga/reset_manager_arria10.c +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -109,8 +109,8 @@ int socfpga_reset_deassert_bridges_handoff(void) mask_noc, false, 1000, false); } -/* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */ -void socfpga_reset_deassert_osc1wd0(void) +/* Release Watchdog 0 from reset through reset manager */ +void socfpga_reset_deassert_wd0(void) { clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST, ALT_RSTMGR_PER1MODRST_WD0_SET_MSK); diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index ec67a5b0eb..96bad162df 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -263,8 +263,8 @@ void board_init_f(ulong dummy) cm_basic_init(gd->fdt_blob); #ifdef CONFIG_HW_WATCHDOG - /* release osc1 watchdog timer 0 from reset */ - socfpga_reset_deassert_osc1wd0(); + /* release watchdog 0 from reset */ + socfpga_reset_deassert_wd0(); /* reconfigure and enable the watchdog */ hw_watchdog_init();