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ARM: socfpga: Add NAND register address and data register

Message ID 20220912131916.10767-1-teik.heng.chong@intel.com
State Needs Review / ACK, archived
Delegated to: Marek Vasut
Headers show
Series ARM: socfpga: Add NAND register address and data register | expand

Commit Message

Chong, Teik Heng Sept. 12, 2022, 1:19 p.m. UTC 
From: Tien Fong Chee <tien.fong.chee@intel.com>

These are required by NAND init in SPL.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 2 ++
 1 file changed, 2 insertions(+)
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Patch

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index b947cc0729..120cbfa23a 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -12,6 +12,8 @@ 
 #define SOCFPGA_SDMMC_ADDRESS			0xff808000
 #define SOCFPGA_QSPIREGS_ADDRESS		0xff809000
 #define SOCFPGA_QSPIDATA_ADDRESS		0xffa00000
+#define SOCFPGA_NANDREGS_ADDRESS		0xffb80000
+#define SOCFPGA_NANDDATA_ADDRESS		0xffb90000
 #define SOCFPGA_UART1_ADDRESS			0xffc02100
 #define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xffcfa000
 #define SOCFPGA_FPGAMGRDATA_ADDRESS		0xffcfe400