| Message ID | 20220804104156.22209-1-pali@kernel.org |
|---|---|
| State | Accepted |
| Commit | 7a1c07117372c746258f79e035dc188fe52c1b48 |
| Delegated to: | Stefan Roese |
| Headers | show |
| Series | [u-boot-marvell,1/3] arm64: a37xx: pinctrl: Fix definitions for MPP pins 20-22 | expand |
On 04.08.22 12:41, Pali Rohár wrote: > All 3 MPP pins (20, 21 and 22) can be configured individually and also can > be configured to GPIO functions. Fix definitions for these MPP pins in > existing pin groups. After this change GPIO function can be enabled just > for one of these 3 pins. > > Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Thanks, Stefan > --- > drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c > index bb7a76baed1f..a5407a16ee36 100644 > --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c > +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c > @@ -200,9 +200,11 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { > PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */ > PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), > PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), > - PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), > - PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"), > - PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"), > + PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"), > + PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12), > + "ptp", "mii"), > + PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13), > + "ptp", "mii"), > PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14), > "mii", "mii_err"), > }; Viele Grüße, Stefan Roese
On 04.08.22 12:41, Pali Rohár wrote: > All 3 MPP pins (20, 21 and 22) can be configured individually and also can > be configured to GPIO functions. Fix definitions for these MPP pins in > existing pin groups. After this change GPIO function can be enabled just > for one of these 3 pins. > > Signed-off-by: Pali Rohár <pali@kernel.org> Applied to u-boot-marvell/master Thanks, Stefan > --- > drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c > index bb7a76baed1f..a5407a16ee36 100644 > --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c > +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c > @@ -200,9 +200,11 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { > PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */ > PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), > PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), > - PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), > - PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"), > - PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"), > + PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"), > + PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12), > + "ptp", "mii"), > + PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13), > + "ptp", "mii"), > PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14), > "mii", "mii_err"), > }; Viele Grüße, Stefan Roese
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index bb7a76baed1f..a5407a16ee36 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -200,9 +200,11 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */ PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), - PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), - PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"), - PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"), + PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"), + PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12), + "ptp", "mii"), + PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13), + "ptp", "mii"), PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14), "mii", "mii_err"), };
All 3 MPP pins (20, 21 and 22) can be configured individually and also can be configured to GPIO functions. Fix definitions for these MPP pins in existing pin groups. After this change GPIO function can be enabled just for one of these 3 pins. Signed-off-by: Pali Rohár <pali@kernel.org> --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)