| Message ID | 20220802135450.25057-1-jit.loon.lim@intel.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
| Series | None | expand |
Hi Jit Loon, > -----Original Message----- > From: Lim, Jit Loon <jit.loon.lim@intel.com> > Sent: Tuesday, 2 August, 2022 9:55 PM > To: u-boot@lists.denx.de > Cc: Jagan Teki <jagan@amarulasolutions.com>; Vignesh R <vigneshr@ti.com>; > Vasut, Marek <marex@denx.de>; Simon <simon.k.r.goldschmidt@gmail.com>; > Chaplin, Kris <kris.chaplin@intel.com>; Chee, Tien Fong > <tien.fong.chee@intel.com>; Hea, Kok Kiang <kok.kiang.hea@intel.com>; Lim, > Elly Siew Chin <elly.siew.chin.lim@intel.com>; Kho, Sin Hui > <sin.hui.kho@intel.com>; Lokanathan, Raaj <raaj.lokanathan@intel.com>; > Maniyam, Dinesh <dinesh.maniyam@intel.com>; Ng, Boon Khai > <boon.khai.ng@intel.com>; Yuslaimi, Alif Zakuan > <alif.zakuan.yuslaimi@intel.com>; Chong, Teik Heng > <teik.heng.chong@intel.com>; Zamri, Muhammad Hazim Izzat > <muhammad.hazim.izzat.zamri@intel.com>; Lim, Jit Loon > <jit.loon.lim@intel.com>; Chee Hong Ang <chee.hong.ang@intel.com> > Subject: [PATCH 016/347] FogBugz #516535: Fix QSPI write issues Please drop the "[PATCH 016/347]" and replace "FogBugz #516535" with appropriate tag. > > From: Chee Hong Ang <chee.hong.ang@intel.com> > > QSPI driver perform chip select on every flash read/write access. The driver need > to disable/enable the QSPI controller while performing chip select. This may > cause some data lost especially the QSPI controller is configured to run at > slower speed as it may take longer time to access the flash device. > This patch prevent the driver from disable/enable the QSPI controller too soon > and inadvertently halting any ongoing flash read/write access by ensuring the > QSPI controller is always in idle mode after each read/write access. > > Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> > --- > drivers/spi/cadence_qspi_apb.c | 15 ++++++++------- > 1 file changed, 8 insertions(+), 7 deletions(-) > > diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c > index 2cdf4c9c9f..5e03495f45 100644 > --- a/drivers/spi/cadence_qspi_apb.c > +++ b/drivers/spi/cadence_qspi_apb.c > @@ -858,13 +858,9 @@ cadence_qspi_apb_indirect_read_execute(struct > cadence_spi_plat *plat, > writel(CQSPI_REG_INDIRECTRD_DONE, > plat->regbase + CQSPI_REG_INDIRECTRD); > > - /* Check indirect done status */ > - ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD, > - CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0); > - if (ret) { > - printf("Indirect read clear completion error (%i)\n", ret); > - goto failrd; > - } > + /* Wait til QSPI is idle */ > + if (!cadence_qspi_wait_idle(plat->regbase)) > + return -EIO; > > return 0; > > @@ -1031,6 +1027,11 @@ cadence_qspi_apb_indirect_write_execute(struct > cadence_spi_plat *plat, > > if (bounce_buf) > free(bounce_buf); > + > + /* Wait til QSPI is idle */ > + if (!cadence_qspi_wait_idle(plat->regbase)) > + return -EIO; > + > return 0; > > failwr: > -- > 2.25.1 Regards, Tien Fong
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 2cdf4c9c9f..5e03495f45 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -858,13 +858,9 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat, writel(CQSPI_REG_INDIRECTRD_DONE, plat->regbase + CQSPI_REG_INDIRECTRD); - /* Check indirect done status */ - ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD, - CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0); - if (ret) { - printf("Indirect read clear completion error (%i)\n", ret); - goto failrd; - } + /* Wait til QSPI is idle */ + if (!cadence_qspi_wait_idle(plat->regbase)) + return -EIO; return 0; @@ -1031,6 +1027,11 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat, if (bounce_buf) free(bounce_buf); + + /* Wait til QSPI is idle */ + if (!cadence_qspi_wait_idle(plat->regbase)) + return -EIO; + return 0; failwr: