[17/21] ls1021aqds/ls1021aiot: Remove legacy non-DM_ETH code

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 7c93d30e1d2a..377c6aa077dc 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -41,7 +41,6 @@  obj-$(CONFIG_PQ_MDS_PIB)	+= pq-mds-pib.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ID_EEPROM)	+= sys_eeprom.o
 endif
-obj-$(CONFIG_FSL_SGMII_RISER)	+= sgmii_riser.o
 ifndef CONFIG_RAMBOOT_PBL
 obj-$(CONFIG_FSL_FIXED_MMC_LOCATION)	+= sdhc_boot.o
 endif
diff --git a/board/freescale/common/sgmii_riser.c b/board/freescale/common/sgmii_riser.c
deleted file mode 100644
index 23157930101f..000000000000
--- a/board/freescale/common/sgmii_riser.c
+++ /dev/null
@@ -1,130 +0,0 @@ 
-/*
- * Freescale SGMII Riser Card
- *
- * This driver supports the SGMII Riser card found on the
- * "DS" style of development board from Freescale.
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- */
-
-#include <config.h>
-#include <common.h>
-#include <log.h>
-#include <net.h>
-#include <linux/libfdt.h>
-#include <tsec.h>
-#include <fdt_support.h>
-
-void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num)
-{
-	int i;
-
-	for (i = 0; i < num; i++)
-		if (tsec_info[i].flags & TSEC_SGMII)
-			tsec_info[i].phyaddr += SGMII_RISER_PHY_OFFSET;
-}
-
-void fsl_sgmii_riser_fdt_fixup(void *fdt)
-{
-	struct eth_device *dev;
-	int node;
-	int mdio_node;
-	int i = -1;
-	int etsec_num = 0;
-
-	node = fdt_path_offset(fdt, "/aliases");
-	if (node < 0)
-		return;
-
-	while ((dev = eth_get_dev_by_index(++i)) != NULL) {
-		struct tsec_private *priv;
-		int phy_node;
-		int enet_node;
-		uint32_t ph;
-		char sgmii_phy[16];
-		char enet[16];
-		const u32 *phyh;
-		const char *model;
-		const char *path;
-
-		if (!strstr(dev->name, "eTSEC"))
-			continue;
-
-		priv = dev->priv;
-		if (!(priv->flags & TSEC_SGMII)) {
-			etsec_num++;
-			continue;
-		}
-
-		mdio_node = fdt_node_offset_by_compatible(fdt, -1,
-				"fsl,gianfar-mdio");
-		if (mdio_node < 0)
-			return;
-
-		sprintf(sgmii_phy, "sgmii-phy@%d", etsec_num);
-		phy_node = fdt_subnode_offset(fdt, mdio_node, sgmii_phy);
-		if (phy_node > 0) {
-			fdt_increase_size(fdt, 32);
-			ph = fdt_create_phandle(fdt, phy_node);
-			if (!ph)
-				continue;
-		}
-
-		sprintf(enet, "ethernet%d", etsec_num++);
-		path = fdt_getprop(fdt, node, enet, NULL);
-		if (!path) {
-			debug("No alias for %s\n", enet);
-			continue;
-		}
-
-		enet_node = fdt_path_offset(fdt, path);
-		if (enet_node < 0)
-			continue;
-
-		model = fdt_getprop(fdt, enet_node, "model", NULL);
-
-		/*
-		 * We only want to do this to eTSECs.  On some platforms
-		 * there are more than one type of gianfar-style ethernet
-		 * controller, and as we are creating an implicit connection
-		 * between ethernet nodes and eTSEC devices, it is best to
-		 * make the connection use as much explicit information
-		 * as exists.
-		 */
-		if (!strstr(model, "TSEC"))
-			continue;
-
-		if (phy_node < 0) {
-			/*
-			 * This part is only for old device tree without
-			 * sgmii_phy nodes. It's kept just for compatible
-			 * reason. Soon to be deprecated if all device tree
-			 * get updated.
-			 */
-			phyh = fdt_getprop(fdt, enet_node, "phy-handle", NULL);
-			if (!phyh)
-				continue;
-
-			phy_node = fdt_node_offset_by_phandle(fdt,
-					fdt32_to_cpu(*phyh));
-
-			priv = dev->priv;
-
-			if (priv->flags & TSEC_SGMII)
-				fdt_setprop_cell(fdt, phy_node, "reg",
-						priv->phyaddr);
-		} else {
-			fdt_setprop(fdt, enet_node, "phy-handle", &ph,
-					sizeof(ph));
-			fdt_setprop_string(fdt, enet_node,
-					"phy-connection-type",
-					phy_string_for_interface(
-						PHY_INTERFACE_MODE_SGMII));
-		}
-	}
-}
diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c
index 5ab03b334041..3ed6100b7cf0 100644
--- a/board/freescale/ls1021aiot/ls1021aiot.c
+++ b/board/freescale/ls1021aiot/ls1021aiot.c
@@ -109,44 +109,6 @@  int dram_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_TSEC_ENET
-int board_eth_init(struct bd_info *bis)
-{
-	struct fsl_pq_mdio_info mdio_info;
-	struct tsec_info_struct tsec_info[4];
-	int num = 0;
-
-#ifdef CONFIG_TSEC1
-	SET_STD_TSEC_INFO(tsec_info[num], 1);
-	if (is_serdes_configured(SGMII_TSEC1)) {
-		puts("eTSEC1 is in sgmii mode.\n");
-		tsec_info[num].flags |= TSEC_SGMII;
-	}
-	num++;
-#endif
-#ifdef CONFIG_TSEC2
-	SET_STD_TSEC_INFO(tsec_info[num], 2);
-	if (is_serdes_configured(SGMII_TSEC2)) {
-		puts("eTSEC2 is in sgmii mode.\n");
-		tsec_info[num].flags |= TSEC_SGMII;
-	}
-	num++;
-#endif
-	if (!num) {
-		printf("No TSECs initialized\n");
-		return 0;
-	}
-
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-	mdio_info.name = DEFAULT_MII_NAME;
-	fsl_pq_mdio_init(bis, &mdio_info);
-
-	tsec_eth_init(bis, tsec_info, num);
-
-	return pci_eth_init(bis);
-}
-#endif
-
 int board_early_init_f(void)
 {
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile
index 65030342be3c..8cbf33fa0cef 100644
--- a/board/freescale/ls1021aqds/Makefile
+++ b/board/freescale/ls1021aqds/Makefile
@@ -6,5 +6,4 @@ 
 
 obj-y += ls1021aqds.o
 obj-y += ddr.o
-obj-y += eth.o
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/board/freescale/ls1021aqds/eth.c b/board/freescale/ls1021aqds/eth.c
deleted file mode 100644
index a9f162b974d4..000000000000
--- a/board/freescale/ls1021aqds/eth.c
+++ /dev/null
@@ -1,186 +0,0 @@ 
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * This file handles the board muxing between the RGMII/SGMII PHYs on
- * Freescale LS1021AQDS board. The RGMII PHYs are the three on-board 1Gb
- * ports. The SGMII PHYs are provided by the standard Freescale four-port
- * SGMII riser card.
- *
- * Muxing is handled via the PIXIS BRDCFG4 register. The EMI1 bits control
- * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII depends
- * on which port is used. The value for SGMII depends on which slot the riser
- * is inserted in.
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/arch/fsl_serdes.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <malloc.h>
-
-#include "../common/sgmii_riser.h"
-#include "../common/qixis.h"
-
-#define EMI1_MASK       0x1f
-#define EMI1_RGMII0     1
-#define EMI1_RGMII1     2
-#define EMI1_RGMII2     3
-#define EMI1_SGMII1     0x1c
-#define EMI1_SGMII2     0x1d
-
-struct ls1021a_mdio {
-	struct mii_dev *realbus;
-};
-
-static void ls1021a_mux_mdio(int addr)
-{
-	u8 brdcfg4;
-
-	brdcfg4 = QIXIS_READ(brdcfg[4]);
-	brdcfg4 &= EMI1_MASK;
-
-	switch (addr) {
-	case EMI1_RGMII0:
-		brdcfg4 |= 0;
-		break;
-	case EMI1_RGMII1:
-		brdcfg4 |= 0x20;
-		break;
-	case EMI1_RGMII2:
-		brdcfg4 |= 0x40;
-		break;
-	case EMI1_SGMII1:
-		brdcfg4 |= 0x60;
-		break;
-	case EMI1_SGMII2:
-		brdcfg4 |= 0x80;
-		break;
-	default:
-		brdcfg4 |= 0xa0;
-		break;
-	}
-
-	QIXIS_WRITE(brdcfg[4], brdcfg4);
-}
-
-static int ls1021a_mdio_read(struct mii_dev *bus, int addr, int devad,
-			     int regnum)
-{
-	struct ls1021a_mdio *priv = bus->priv;
-
-	ls1021a_mux_mdio(addr);
-
-	return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int ls1021a_mdio_write(struct mii_dev *bus, int addr, int devad,
-			      int regnum, u16 value)
-{
-	struct ls1021a_mdio *priv = bus->priv;
-
-	ls1021a_mux_mdio(addr);
-
-	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int ls1021a_mdio_reset(struct mii_dev *bus)
-{
-	struct ls1021a_mdio *priv = bus->priv;
-
-	return priv->realbus->reset(priv->realbus);
-}
-
-static int ls1021a_mdio_init(char *realbusname, char *fakebusname)
-{
-	struct ls1021a_mdio *lsmdio;
-	struct mii_dev *bus = mdio_alloc();
-
-	if (!bus) {
-		printf("Failed to allocate LS102xA MDIO bus\n");
-		return -1;
-	}
-
-	lsmdio = malloc(sizeof(*lsmdio));
-	if (!lsmdio) {
-		printf("Failed to allocate LS102xA private data\n");
-		free(bus);
-		return -1;
-	}
-
-	bus->read = ls1021a_mdio_read;
-	bus->write = ls1021a_mdio_write;
-	bus->reset = ls1021a_mdio_reset;
-	strcpy(bus->name, fakebusname);
-
-	lsmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
-	if (!lsmdio->realbus) {
-		printf("No bus with name %s\n", realbusname);
-		free(bus);
-		free(lsmdio);
-		return -1;
-	}
-
-	bus->priv = lsmdio;
-
-	return mdio_register(bus);
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	struct fsl_pq_mdio_info mdio_info;
-	struct tsec_info_struct tsec_info[3];
-	int num = 0;
-
-#ifdef CONFIG_TSEC1
-	SET_STD_TSEC_INFO(tsec_info[num], 1);
-	if (is_serdes_configured(SGMII_TSEC1)) {
-		puts("eTSEC1 is in sgmii mode\n");
-		tsec_info[num].flags |= TSEC_SGMII;
-		tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO";
-	} else {
-		tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO";
-	}
-	num++;
-#endif
-#ifdef CONFIG_TSEC2
-	SET_STD_TSEC_INFO(tsec_info[num], 2);
-	if (is_serdes_configured(SGMII_TSEC2)) {
-		puts("eTSEC2 is in sgmii mode\n");
-		tsec_info[num].flags |= TSEC_SGMII;
-		tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO";
-	} else {
-		tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO";
-	}
-	num++;
-#endif
-#ifdef CONFIG_TSEC3
-	SET_STD_TSEC_INFO(tsec_info[num], 3);
-	tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO";
-	num++;
-#endif
-	if (!num) {
-		printf("No TSECs initialized\n");
-		return 0;
-	}
-
-#ifdef CONFIG_FSL_SGMII_RISER
-	fsl_sgmii_riser_init(tsec_info, num);
-#endif
-
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-	mdio_info.name = DEFAULT_MII_NAME;
-
-	fsl_pq_mdio_init(bis, &mdio_info);
-
-	/* Register the virtual MDIO front-ends */
-	ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_RGMII_MDIO");
-	ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_SGMII_MDIO");
-
-	tsec_eth_init(bis, tsec_info, num);
-
-	return pci_eth_init(bis);
-}
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index d9a973c13fba..aaf28a346d05 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -285,14 +285,6 @@ 
 #define TSEC1_PHYIDX			0
 #define TSEC2_PHYIDX			0
 #define TSEC3_PHYIDX			0
-
-#define CONFIG_FSL_SGMII_RISER		1
-#define SGMII_RISER_PHY_OFFSET		0x1b
-
-#ifdef CONFIG_FSL_SGMII_RISER
-#define CONFIG_SYS_TBIPA_VALUE		8
-#endif
-
 #endif
 
 #define CONFIG_PEN_ADDR_BIG_ENDIAN