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[65.184.195.139]) by smtp.gmail.com with ESMTPSA id bj3-20020a05620a190300b006b5ee4de4fbsm2056095qkb.37.2022.07.31.18.08.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jul 2022 18:08:31 -0700 (PDT) From: Tom Rini To: u-boot@lists.denx.de Subject: [PATCH 3/8] Remove CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR et al Date: Sun, 31 Jul 2022 21:08:24 -0400 Message-Id: <20220801010829.3177443-3-trini@konsulko.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220801010829.3177443-1-trini@konsulko.com> References: <20220801010829.3177443-1-trini@konsulko.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean This removes the following symbols: CONFIG_SYS_FSL_DSPI_BE CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET CONFIG_SYS_FSL_DSP_DDR_ADDR CONFIG_SYS_FSL_DSP_M2_RAM_ADDR CONFIG_SYS_FSL_DSP_M3_RAM_ADDR CONFIG_SYS_FSL_ERRATUM_A008751 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT CONFIG_SYS_FSL_ESDHC_NUM CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET CONFIG_SYS_FSL_ISBC_VER CONFIG_SYS_FSL_QSPI_LE CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SRDS_NUM_PLLS CONFIG_SYS_FSL_WDOG_BE CONFIG_SYS_GP1DIR CONFIG_SYS_GP1ODR CONFIG_SYS_GP2DIR CONFIG_SYS_GP2ODR CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HMI_BASE FSL_QSPI_FLASH_NUM FSL_QSPI_FLASH_SIZE Signed-off-by: Tom Rini --- README | 15 --------------- arch/arm/include/asm/arch-fsl-layerscape/config.h | 5 ----- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ------ arch/arm/include/asm/arch-ls102xa/config.h | 3 --- arch/m68k/cpu/mcf52x2/start.S | 4 ---- arch/m68k/cpu/mcf530x/start.S | 4 ---- arch/powerpc/include/asm/config_mpc85xx.h | 10 ---------- arch/powerpc/include/asm/immap_85xx.h | 13 ------------- include/configs/P2041RDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/bk4r1.h | 7 ------- include/configs/corenet_ds.h | 1 - include/configs/eb_cpu5282.h | 2 -- include/configs/km/km-mpc8309.h | 5 ----- include/configs/ls1021atsn.h | 4 ---- include/configs/m53menlo.h | 1 - include/configs/mx51evk.h | 1 - include/configs/mx53cx9020.h | 1 - include/configs/mx53loco.h | 1 - include/configs/socrates.h | 1 - include/configs/usbarmory.h | 1 - include/configs/vf610twr.h | 1 - 24 files changed, 90 deletions(-) diff --git a/README b/README index ff0534137716..05c84141ebbe 100644 --- a/README +++ b/README @@ -330,21 +330,6 @@ The following options need to be configured: This is the value to write into CCSR offset 0x18600 according to the A004510 workaround. - CONFIG_SYS_FSL_DSP_DDR_ADDR - This value denotes start offset of DDR memory which is - connected exclusively to the DSP cores. - - CONFIG_SYS_FSL_DSP_M2_RAM_ADDR - This value denotes start offset of M2 memory - which is directly connected to the DSP core. - - CONFIG_SYS_FSL_DSP_M3_RAM_ADDR - This value denotes start offset of M3 memory which is directly - connected to the DSP core. - - CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT - This value denotes start offset of DSP CCSR space. - CONFIG_SYS_FSL_SINGLE_SOURCE_CLK Single Source Clock is clocking mode present in some of FSL SoC's. In this mode, a single differential clock is used to supply diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 1791b978704d..587d585412bb 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -94,8 +94,6 @@ #define EPU_EPCTR5 0x700060a14ULL #define EPU_EPGCR 0x700060000ULL -#define CONFIG_SYS_FSL_ERRATUM_A008751 - #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #elif defined(CONFIG_ARCH_LS1088A) @@ -218,9 +216,6 @@ #define DCSR_DCFG_SBEESR2 0x20140534 #define DCSR_DCFG_MBEESR2 0x20140544 -#define CONFIG_SYS_FSL_WDOG_BE -#define CONFIG_SYS_FSL_DSPI_BE - /* SoC related */ #ifdef CONFIG_ARCH_LS1043A #define CONFIG_SYS_FSL_QMAN_V3 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index f2dbcdc8164f..1fb1191a65ea 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -166,12 +166,6 @@ struct sys_info { }; #define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000 -#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000 -#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000 -#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000 -#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000 -#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000 -#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 #define CONFIG_SYS_FSL_FM1_ADDR \ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 868456f1f139..1b2be8fcde79 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -79,9 +79,6 @@ #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #endif -#define CONFIG_SYS_FSL_WDOG_BE -#define CONFIG_SYS_FSL_DSPI_BE - #define DCU_LAYER_MAX_NUM 16 #ifdef CONFIG_ARCH_LS1021A diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S index d3cdc4217617..4488a6e4c7fb 100644 --- a/arch/m68k/cpu/mcf52x2/start.S +++ b/arch/m68k/cpu/mcf52x2/start.S @@ -303,10 +303,6 @@ clear_bss: /* set parameters for board_init_r */ move.l %a0,-(%sp) /* dest_addr */ move.l %d0,-(%sp) /* gd */ -#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \ - defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP) - halt -#endif jsr (%a1) /******************************************************************************/ diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S index 0daff5d0c4cf..287e8e7873c5 100644 --- a/arch/m68k/cpu/mcf530x/start.S +++ b/arch/m68k/cpu/mcf530x/start.S @@ -226,10 +226,6 @@ clear_bss: /* set parameters for board_init_r */ move.l %a0,-(%sp) /* dest_addr */ move.l %d0,-(%sp) /* gd */ -#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE!=CONFIG_SYS_INT_FLASH_BASE) && \ - defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP) - halt -#endif jsr (%a1) /******************************************************************************/ diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 458c0a8d3653..543b0c55358e 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -137,19 +137,12 @@ #elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 -#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #elif defined(CONFIG_ARCH_BSC9132) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 -#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 -#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 -#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 -#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #elif defined(CONFIG_ARCH_T4240) @@ -202,7 +195,6 @@ #ifdef CONFIG_ARCH_B4860 #define CONFIG_MAX_DSP_CPUS 12 #define CONFIG_NUM_DSP_CPUS 6 -#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 @@ -212,7 +204,6 @@ #define CONFIG_SYS_FSL_SRIO_LIODN #else #define CONFIG_MAX_DSP_CPUS 2 -#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 0 @@ -288,7 +279,6 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ISBC_VER 2 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index b8bc58448217..7e88779227a4 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1464,7 +1464,6 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080 -#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 @@ -1477,8 +1476,6 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000 #define FSL_CORENET_RCWSR13_EC2 0x0c000000 #define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000 -#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 -#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00 #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 @@ -2576,20 +2573,10 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 -#if defined(CONFIG_ARCH_BSC9132) -#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000 -#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \ - (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET) -#endif - #define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) #define CONFIG_SYS_FSL_SCFG_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET) -#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \ - (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET) -#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \ - (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET) #define CONFIG_SYS_FSL_QMAN_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) #define CONFIG_SYS_FSL_BMAN_ADDR \ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index de5f42b10117..1ba48e587215 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -326,7 +326,6 @@ #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #endif /* diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 3da9831a028e..9d43d87338a9 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -434,7 +434,6 @@ */ #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #endif /* diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 813d8fae9c8c..9a9920a88055 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -391,7 +391,6 @@ */ #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #endif /* diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 332f34e1ff22..4280c2df1fab 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -397,7 +397,6 @@ #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #endif diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index 925a68787c91..b3e1fddc02fc 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -55,13 +55,6 @@ #define IMX_FEC1_BASE ENET1_BASE_ADDR -/* QSPI Configs*/ -#ifdef CONFIG_FSL_QSPI -#define FSL_QSPI_FLASH_SIZE (SZ_16M) -#define FSL_QSPI_FLASH_NUM 2 -#define CONFIG_SYS_FSL_QSPI_LE -#endif - /* boot command, including the target-defined one if any */ /* Extra env settings (including the target-defined ones if any) */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index a4fb2b53dc9f..5f3fd89c21bb 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -319,7 +319,6 @@ #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #endif /* diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 249da66237b5..79cacd7dacc6 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -8,8 +8,6 @@ #ifndef _CONFIG_EB_CPU5282_H_ #define _CONFIG_EB_CPU5282_H_ -#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP - /*----------------------------------------------------------------------* * High Level Configuration Options (easy to change) * *----------------------------------------------------------------------*/ diff --git a/include/configs/km/km-mpc8309.h b/include/configs/km/km-mpc8309.h index af35e8e79267..0468ed5e831a 100644 --- a/include/configs/km/km-mpc8309.h +++ b/include/configs/km/km-mpc8309.h @@ -49,11 +49,6 @@ /* GPR_1 */ #define CONFIG_SYS_GPR1 0x50008060 -#define CONFIG_SYS_GP1DIR 0x00000000 -#define CONFIG_SYS_GP1ODR 0x00000000 -#define CONFIG_SYS_GP2DIR 0xFF000000 -#define CONFIG_SYS_GP2ODR 0x00000000 - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 2fbd495e1193..f318eb58603d 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -75,10 +75,6 @@ #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -/* QSPI */ -#define FSL_QSPI_FLASH_SIZE (1 << 24) -#define FSL_QSPI_FLASH_NUM 2 - /* PCIe */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index b3348bc63bb9..0499e633512b 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -38,7 +38,6 @@ */ #ifdef CONFIG_CMD_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 #endif /* diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index a423dd28b07d..fbc9a0416938 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -35,7 +35,6 @@ * MMC Configs * */ #define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR -#define CONFIG_SYS_FSL_ESDHC_NUM 2 /* USB Configs */ #define CONFIG_MXC_USB_PORT 1 diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index f1d751f15a24..d58d1534a3bd 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -18,7 +18,6 @@ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 2 /* bootz: zImage/initrd.img support */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 9ceed12e4872..60ec34cf8e06 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -15,7 +15,6 @@ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 2 /* USB Configs */ #define CONFIG_MXC_USB_PORT 1 diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 498deb4e3fc7..762ba44542d3 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -103,7 +103,6 @@ /* FPGA and NAND */ #define CONFIG_SYS_FPGA_BASE 0xc0000000 #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ -#define CONFIG_SYS_HMI_BASE 0xc0010000 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 2632d56cb1c2..08a6f5fbccdc 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -21,7 +21,6 @@ /* SD/MMC */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 /* USB */ #define CONFIG_MXC_USB_PORT 1 diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 32d9df0a00ce..c13f2ba196e6 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -21,7 +21,6 @@ #endif #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 #define CONFIG_FEC_MXC_PHYADDR 0