@@ -1230,6 +1230,9 @@ config SYS_CPC_REINIT_F
config SYS_FSL_CPC
bool "Corenet Platform Cache support"
+config SYS_CACHE_STASHING
+ bool "Enable cache stashing"
+
config SYS_MPC85XX_NO_RESETVEC
bool "Discard resetvec section and move bootpg section up"
depends on MPC85xx
@@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -15,6 +15,7 @@ CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
@@ -16,6 +16,7 @@ CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
@@ -18,6 +18,7 @@ CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
@@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -14,6 +14,7 @@ CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
@@ -15,6 +15,7 @@ CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
@@ -17,6 +17,7 @@ CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
@@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -14,6 +14,7 @@ CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
@@ -15,6 +15,7 @@ CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
@@ -8,6 +8,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_NXP_ESBC=y
CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000
CONFIG_PCIE1=y
@@ -17,6 +17,7 @@ CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
@@ -9,6 +9,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_SRIO_PCIE_BOOT_SLAVE=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
@@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -14,6 +14,7 @@ CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
@@ -15,6 +15,7 @@ CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
@@ -17,6 +17,7 @@ CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
@@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -14,6 +14,7 @@ CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
@@ -15,6 +15,7 @@ CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
CONFIG_PCIE1=y
@@ -17,6 +17,7 @@ CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
CONFIG_PCIE1=y
@@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_T2080RDB_REV_D=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
@@ -15,6 +15,7 @@ CONFIG_TARGET_T4240RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
@@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@@ -13,6 +13,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
+CONFIG_SYS_CACHE_STASHING=y
# CONFIG_DEEP_SLEEP is not set
CONFIG_PCIE1=y
CONFIG_KM_DEF_NETDEV="eth2"
@@ -45,7 +45,6 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
@@ -95,7 +95,6 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
@@ -63,7 +63,6 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
@@ -68,7 +68,6 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_CACHE_STASHING
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
@@ -63,7 +63,6 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_CACHE_STASHING
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
@@ -44,7 +44,6 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_CACHE_STASHING
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
@@ -38,7 +38,6 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
@@ -146,7 +146,6 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
/* POST memory regions test */
@@ -497,7 +497,6 @@ CONFIG_SYS_CACHE_ACR1
CONFIG_SYS_CACHE_ACR2
CONFIG_SYS_CACHE_DCACR
CONFIG_SYS_CACHE_ICACR
-CONFIG_SYS_CACHE_STASHING
CONFIG_SYS_CCSRBAR
CONFIG_SYS_CCSRBAR_PHYS
CONFIG_SYS_CCSRBAR_PHYS_HIGH
This converts the following to Kconfig: CONFIG_SYS_CACHE_STASHING Signed-off-by: Tom Rini <trini@konsulko.com> --- arch/powerpc/cpu/mpc85xx/Kconfig | 3 +++ configs/P2041RDB_NAND_defconfig | 1 + configs/P2041RDB_SDCARD_defconfig | 1 + configs/P2041RDB_SPIFLASH_defconfig | 1 + configs/P2041RDB_defconfig | 1 + configs/P3041DS_NAND_defconfig | 1 + configs/P3041DS_SDCARD_defconfig | 1 + configs/P3041DS_SPIFLASH_defconfig | 1 + configs/P3041DS_defconfig | 1 + configs/P4080DS_SDCARD_defconfig | 1 + configs/P4080DS_SPIFLASH_defconfig | 1 + configs/P4080DS_defconfig | 1 + configs/P5040DS_NAND_defconfig | 1 + configs/P5040DS_SDCARD_defconfig | 1 + configs/P5040DS_SPIFLASH_defconfig | 1 + configs/P5040DS_defconfig | 1 + configs/T1024RDB_NAND_defconfig | 1 + configs/T1024RDB_SDCARD_defconfig | 1 + configs/T1024RDB_SPIFLASH_defconfig | 1 + configs/T1024RDB_defconfig | 1 + configs/T1042D4RDB_NAND_defconfig | 1 + configs/T1042D4RDB_SDCARD_defconfig | 1 + configs/T1042D4RDB_SPIFLASH_defconfig | 1 + configs/T1042D4RDB_defconfig | 1 + configs/T2080QDS_NAND_defconfig | 1 + configs/T2080QDS_SDCARD_defconfig | 1 + configs/T2080QDS_SECURE_BOOT_defconfig | 1 + configs/T2080QDS_SPIFLASH_defconfig | 1 + configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 1 + configs/T2080QDS_defconfig | 1 + configs/T2080RDB_NAND_defconfig | 1 + configs/T2080RDB_SDCARD_defconfig | 1 + configs/T2080RDB_SPIFLASH_defconfig | 1 + configs/T2080RDB_defconfig | 1 + configs/T2080RDB_revD_NAND_defconfig | 1 + configs/T2080RDB_revD_SDCARD_defconfig | 1 + configs/T2080RDB_revD_SPIFLASH_defconfig | 1 + configs/T2080RDB_revD_defconfig | 1 + configs/T4240RDB_SDCARD_defconfig | 1 + configs/T4240RDB_defconfig | 1 + configs/kmcent2_defconfig | 1 + include/configs/P2041RDB.h | 1 - include/configs/T102xRDB.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/corenet_ds.h | 1 - include/configs/kmcent2.h | 1 - scripts/config_whitelist.txt | 1 - 50 files changed, 43 insertions(+), 9 deletions(-)