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[31.182.204.250]) by smtp.gmail.com with ESMTPSA id a17-20020ac25e71000000b00479342519e5sm592379lfr.210.2022.06.17.03.47.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jun 2022 03:48:00 -0700 (PDT) From: =?utf-8?q?Pawe=C5=82_Anikiel?= To: marex@denx.de, simon.k.r.goldschmidt@gmail.com, tien.fong.chee@intel.com, michal.simek@xilinx.com Cc: u-boot@lists.denx.de, sjg@chromium.org, festevam@denx.de, jagan@amarulasolutions.com, andre.przywara@arm.com, narmstrong@baylibre.com, pbrobinson@gmail.com, tharvey@gateworks.com, paul.liu@linaro.org, christianshewitt@gmail.com, adrian.fiergolski@fastree3d.com, marek.behun@nic.cz, wd@denx.de, elly.siew.chin.lim@intel.com, upstream@semihalf.com, amstan@chromium.org, =?utf-8?q?Pawe=C5=82_Anikiel?= Subject: [PATCH v3 10/11] socfpga: arria10: Wait for fifo empty after writing bitstream Date: Fri, 17 Jun 2022 12:47:25 +0200 Message-Id: <20220617104726.158688-11-pan@semihalf.com> X-Mailer: git-send-email 2.36.1.476.g0c4daa206d-goog In-Reply-To: <20220617104726.158688-1-pan@semihalf.com> References: <20220617104726.158688-1-pan@semihalf.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean For some reason, on the Mercury+ AA1 module, calling fpgamgr_wait_early_user_mode immediately after writing the peripheral bitstream leaves the fpga in a broken state (ddr calibration hangs). Adding a delay before the first sync word is written seems to fix this. Inspecting the fpgamgr registers before and after the delay, imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit (instead of a hardcoded delay) also fixes the issue. Signed-off-by: Paweł Anikiel Reviewed-by: Simon Glass --- drivers/fpga/socfpga_arria10.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index 07bfe3060e..d8089122af 100644 --- a/drivers/fpga/socfpga_arria10.c +++ b/drivers/fpga/socfpga_arria10.c @@ -80,6 +80,13 @@ static int wait_for_user_mode(void) 1, FPGA_TIMEOUT_MSEC, false); } +static int wait_for_fifo_empty(void) +{ + return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, + ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK, + 1, FPGA_TIMEOUT_MSEC, false); +} + int is_fpgamgr_early_user_mode(void) { return (readl(&fpga_manager_base->imgcfg_stat) & @@ -874,6 +881,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize, WATCHDOG_RESET(); } + wait_for_fifo_empty(); if (fpga_loadfs.rbfinfo.section == periph_section) { if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {