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[65.184.195.139]) by smtp.gmail.com with ESMTPSA id h14-20020ac8568e000000b00304ef07ee7asm2175625qta.83.2022.06.16.11.04.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jun 2022 11:04:47 -0700 (PDT) From: Tom Rini To: u-boot@lists.denx.de Subject: [PATCH 8/8] Convert CONFIG_SYS_FSL_SFP_BE et al to Kconfig Date: Thu, 16 Jun 2022 14:04:40 -0400 Message-Id: <20220616180440.4181624-8-trini@konsulko.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220616180440.4181624-1-trini@konsulko.com> References: <20220616180440.4181624-1-trini@konsulko.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean This converts the following to Kconfig: CONFIG_KEY_REVOCATION CONFIG_SYS_FSL_SFP_BE CONFIG_SYS_FSL_SFP_LE CONFIG_SYS_FSL_SFP_VER_3_0 CONFIG_SYS_FSL_SFP_VER_3_2 CONFIG_SYS_FSL_SFP_VER_3_4 CONFIG_SYS_FSL_SRK_LE This partly means making sure to enable SYS_FSL_ERRATUM_A007186 only for when CHAIN_OF_TRUST is enabled. Signed-off-by: Tom Rini --- arch/Kconfig.nxp | 33 +++++++++++++++++++ .../include/asm/arch-fsl-layerscape/config.h | 32 ------------------ arch/arm/include/asm/arch-ls102xa/config.h | 3 -- arch/arm/include/asm/fsl_secure_boot.h | 2 -- arch/powerpc/cpu/mpc85xx/Kconfig | 8 ++--- arch/powerpc/include/asm/config_mpc85xx.h | 7 ---- arch/powerpc/include/asm/fsl_secure_boot.h | 5 --- include/fsl_sfp.h | 2 -- 8 files changed, 37 insertions(+), 55 deletions(-) diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp index 015f57f7d0f3..1e26f1dc5372 100644 --- a/arch/Kconfig.nxp +++ b/arch/Kconfig.nxp @@ -33,6 +33,39 @@ config ESBC_ADDR_64BIT help For Layerscape based platforms, ESBC image Address in Header is 64bit. +config SYS_FSL_SFP_BE + def_bool y + depends on CHAIN_OF_TRUST && (PPC || FSL_LSCH2 || ARCH_LS1021A) + +config SYS_FSL_SFP_LE + def_bool y + depends on CHAIN_OF_TRUST && !SYS_FSL_SFP_BE + +choice + prompt "SFP IP revision" + depends on CHAIN_OF_TRUST + default SYS_FSL_SFP_VER_3_0 if PPC + default SYS_FSL_SFP_VER_3_4 + +config SYS_FSL_SFP_VER_3_0 + bool "SFP version 3.0" + +config SYS_FSL_SFP_VER_3_2 + bool "SFP version 3.2" + +config SYS_FSL_SFP_VER_3_4 + bool "SFP version 3.4" + +endchoice + +config SYS_FSL_SRK_LE + def_bool y + depends on CHAIN_OF_TRUST && ARM + +config KEY_REVOCATION + def_bool y + depends on CHAIN_OF_TRUST + config DEEP_SLEEP bool "Enable SoC deep sleep feature" depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index fd41d30c28cd..cd795d6919ac 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -55,11 +55,6 @@ /* SMMU Defintions */ #define SMMU_BASE 0x05000000 /* GR0 Base */ -/* SFP */ -#define CONFIG_SYS_FSL_SFP_VER_3_4 -#define CONFIG_SYS_FSL_SFP_LE -#define CONFIG_SYS_FSL_SRK_LE - /* DCFG - GUR */ #define CONFIG_SYS_FSL_CCSR_GUR_LE @@ -154,11 +149,6 @@ #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN -/* SFP */ -#define CONFIG_SYS_FSL_SFP_VER_3_4 -#define CONFIG_SYS_FSL_SFP_LE -#define CONFIG_SYS_FSL_SRK_LE - /* DCFG - GUR */ #define CONFIG_SYS_FSL_CCSR_GUR_LE #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 @@ -203,11 +193,6 @@ /* SMMU Definitions */ #define SMMU_BASE 0x05000000 /* GR0 Base */ -/* SFP */ -#define CONFIG_SYS_FSL_SFP_VER_3_4 -#define CONFIG_SYS_FSL_SFP_LE -#define CONFIG_SYS_FSL_SRK_LE - /* DCFG - GUR */ #define CONFIG_SYS_FSL_CCSR_GUR_LE @@ -256,11 +241,6 @@ #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN -/* SFP */ -#define CONFIG_SYS_FSL_SFP_VER_3_4 -#define CONFIG_SYS_FSL_SFP_LE -#define CONFIG_SYS_FSL_SRK_LE - /* SEC */ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 @@ -297,10 +277,6 @@ #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_IFC_BE -#define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SRK_LE -#define CONFIG_KEY_REVOCATION /* SMMU Defintions */ #define SMMU_BASE 0x09000000 @@ -336,10 +312,6 @@ #elif defined(CONFIG_ARCH_LS1012A) #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 -#define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SRK_LE -#define CONFIG_KEY_REVOCATION #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE @@ -354,10 +326,6 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #define CONFIG_SYS_FSL_IFC_BE -#define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SRK_LE -#define CONFIG_KEY_REVOCATION /* SMMU Defintions */ #define SMMU_BASE 0x09000000 diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 06ead24bf627..796e2b218e56 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -87,9 +87,6 @@ #define CONFIG_SYS_FSL_ESDHC_BE #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE -#define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SRK_LE #define DCU_LAYER_MAX_NUM 16 diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index d6a7c3dcbd7e..09c88841e0c0 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -21,8 +21,6 @@ #define CONFIG_SPL_UBOOT_KEY_HASH NULL #endif /* ifdef CONFIG_SPL_BUILD */ -#define CONFIG_KEY_REVOCATION - #ifndef CONFIG_SPL_BUILD #ifndef CONFIG_SYS_RAMBOOT /* The key used for verification of next level images diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 2cc0185c3778..0ef5e730bdc2 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -196,7 +196,7 @@ config ARCH_B4420 select SYS_FSL_ERRATUM_A006475 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007075 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 @@ -224,7 +224,7 @@ config ARCH_B4860 select SYS_FSL_ERRATUM_A006475 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007075 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A007907 select SYS_FSL_ERRATUM_A009942 @@ -735,7 +735,7 @@ config ARCH_T2080 select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A007815 select SYS_FSL_ERRATUM_A007907 @@ -768,7 +768,7 @@ config ARCH_T4240 select SYS_FSL_ERRATUM_A006261 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007798 select SYS_FSL_ERRATUM_A007815 select SYS_FSL_ERRATUM_A007907 diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 47b462504799..e82adc6b4545 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -18,7 +18,6 @@ /* IP endianness */ #define CONFIG_SYS_FSL_IFC_BE -#define CONFIG_SYS_FSL_SFP_BE #if defined(CONFIG_ARCH_MPC8548) #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 @@ -199,7 +198,6 @@ #define CONFIG_SYS_FSL_SRIO_LIODN #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_PCI_VER_3_X #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) @@ -216,7 +214,6 @@ #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_SFP_VER_3_0 #ifdef CONFIG_ARCH_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 @@ -264,7 +261,6 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 -#define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_ARCH_T1024) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -291,7 +287,6 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 -#define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_ARCH_T2080) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -321,10 +316,8 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ISBC_VER 2 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE -#define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_ARCH_C29X) diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index e073025ebfb3..9ae4c590f1d5 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -31,7 +31,6 @@ #ifndef CONFIG_SYS_RAMBOOT #define CONFIG_SYS_CPC_REINIT_F #endif -#define CONFIG_KEY_REVOCATION #undef CONFIG_SYS_INIT_L3_ADDR #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 #endif @@ -47,10 +46,6 @@ #endif #endif -#if defined(CONFIG_TARGET_C29XPCIE) -#define CONFIG_KEY_REVOCATION -#endif - #if defined(CONFIG_ARCH_P3041) || \ defined(CONFIG_ARCH_P4080) || \ defined(CONFIG_ARCH_P5040) || \ diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h index 613814d9057c..e7674c1bff2a 100644 --- a/include/fsl_sfp.h +++ b/include/fsl_sfp.h @@ -24,8 +24,6 @@ #define sfp_in32(a) in_be32(a) #define sfp_out32(a, v) out_be32(a, v) #define sfp_in16(a) in_be16(a) -#else -#error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined #endif /* Number of SRKH registers */