From patchwork Wed May 25 08:08:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Raghavendra, Vignesh" X-Patchwork-Id: 1635321 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=ukAC689S; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4L7P164ZVnz9sGH for ; Wed, 25 May 2022 18:11:54 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 79D9D842DC; Wed, 25 May 2022 10:11:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="ukAC689S"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 836CB842DC; Wed, 25 May 2022 10:11:10 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C0A50842DF for ; Wed, 25 May 2022 10:10:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=vigneshr@ti.com Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 24P89uWh007905; Wed, 25 May 2022 03:09:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1653466196; bh=axzn/iQJJJ+8VMXmoZT1zQ89xh1B2pl+h+pKfDh16rA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ukAC689SdjAvyNI5wdcQweGPIymeXjJ/Z6ahu2oc91lZ19KxfzBiyfqH/TeAguMla CDBwuJUIcLfLxpIYPvoH0JnjWzgGyGue7YpqtFF09489/Mt0pg+W0JLzEMrZV+XJKK hh254uKoC291GBFAOZqsD0Qj/CRevocm/ch0XZgc= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 24P89uD9042032 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 May 2022 03:09:56 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Wed, 25 May 2022 03:09:56 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 25 May 2022 03:09:56 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 24P88qPd034515; Wed, 25 May 2022 03:09:51 -0500 From: Vignesh Raghavendra To: Tom Rini , Dave Gerlach , Lukasz Majewski , Sean Anderson , Peng Fan , Jaehoon Chung CC: Simon Glass , Vignesh Raghavendra , Suman Anna , Nishanth Menon , Aswath Govindraju , Bryan Brattlof , , Georgi Vlaev Subject: [PATCH v2 12/12] doc: ti: Add readme for AM62x SK Date: Wed, 25 May 2022 13:38:50 +0530 Message-ID: <20220525080850.94172-13-vigneshr@ti.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220525080850.94172-1-vigneshr@ti.com> References: <20220525080850.94172-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Add info of boot flow and build steps for AM62x SK. Signed-off-by: Vignesh Raghavendra Reviewed-by: Bryan Brattlof --- doc/board/ti/am62x_sk.rst | 231 ++++++++++++++++++++++++++++++++++++++ doc/board/ti/index.rst | 1 + 2 files changed, 232 insertions(+) create mode 100644 doc/board/ti/am62x_sk.rst diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst new file mode 100644 index 0000000000..4e68c2018a --- /dev/null +++ b/doc/board/ti/am62x_sk.rst @@ -0,0 +1,231 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Vignesh Raghavendra + +Texas Instruments AM62 Platforms +================================ + +Introduction: +------------- +The AM62 SoC family is the follow on AM335x built on the K3 Multicore +SoC architecture platform, providing ultra-low-power modes, dual +display, multi-sensor edge compute, security and other BOM-saving +integrations. The AM62 SoC targets a broad market to enable +applications such as Industrial HMI, PLC/CNC/Robot control, Medical +Equipment, Building Automation, Appliances and more. + +Some highlights of this SoC are: + +* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. + Pin-to-pin compatible options for single and quad core are available. +* Cortex-M4F for general-purpose or safety usage. +* Dual display support, providing 24-bit RBG parallel interface and + OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display + resolution. +* Selectable GPU support, up to 8GFLOPS, providing better user experience + in 3D graphic display case and Android. +* PRU(Programmable Realtime Unit) support for customized programmable + interfaces/IOs. +* Integrated Giga-bit Ethernet switch supporting up to a total of two + external ports (TSN capable). +* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for + NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, + 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. +* Dedicated Centralized System Controller for Security, Power, and + Resource Management. +* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, + enabling battery powered system design. + +More details can be found in the Technical Reference Manual: +https://www.ti.com/lit/pdf/spruiv7 + +Boot Flow: +---------- +Below is the pictorial representation of boot flow: + +.. code-block:: text + + +------------------------------------------------------------------------+ + | TIFS | Main R5 | A53 | + +------------------------------------------------------------------------+ + | +--------+ | | | + | | Reset | | | | + | +--------+ | | | + | : | | | + | +--------+ | +-----------+ | | + | | *ROM* |----------|-->| Reset rls | | | + | +--------+ | +-----------+ | | + | | | | : | | + | | ROM | | : | | + | |services| | : | | + | | | | +-------------+ | | + | | | | | *R5 ROM* | | | + | | | | +-------------+ | | + | | |<---------|---|Load and auth| | | + | | | | | tiboot3.bin | | | + | +--------+ | +-------------+ | | + | | |<---------|---| Load sysfw | | | + | | | | | part to TIFS| | | + | | | | | core | | | + | | | | +-------------+ | | + | | | | : | | + | | | | : | | + | | | | : | | + | | | | +-------------+ | | + | | | | | *R5 SPL* | | | + | | | | +-------------+ | | + | | | | | DDR | | | + | | | | | config | | | + | | | | +-------------+ | | + | | | | | Load | | | + | | | | | tispl.bin | | | + | | | | +-------------+ | | + | | | | | Load R5 | | | + | | | | | firmware | | | + | | | | +-------------+ | | + | | |<---------|---| Start A53 | | | + | | | | | and jump to | | | + | | | | | DM fw image | | | + | | | | +-------------+ | | + | | | | | +-----------+ | + | | |----------|-----------------------|---->| Reset rls | | + | | | | | +-----------+ | + | | TIFS | | | : | + | |Services| | | +-----------+ | + | | |<---------|-----------------------|---->|*ATF/OPTEE*| | + | | | | | +-----------+ | + | | | | | : | + | | | | | +-----------+ | + | | |<---------|-----------------------|---->| *A53 SPL* | | + | | | | | +-----------+ | + | | | | | | Load | | + | | | | | | u-boot.img| | + | | | | | +-----------+ | + | | | | | : | + | | | | | +-----------+ | + | | |<---------|-----------------------|---->| *U-Boot* | | + | | | | | +-----------+ | + | | | | | | prompt | | + | | |----------|-----------------------|-----+-----------+-----| + | +--------+ | | | + | | | | + +------------------------------------------------------------------------+ + +- Here TIFS acts as master and provides all the critical services. R5/A53 + requests TIFS to get these services done as shown in the above diagram. + +Sources: +-------- +1. SYSFW: + Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git + Branch: master + +2. ATF: + Tree: https://github.com/ARM-software/arm-trusted-firmware.git + Branch: master + +3. OPTEE: + Tree: https://github.com/OP-TEE/optee_os.git + Branch: master + +4. U-Boot: + Tree: https://source.denx.de/u-boot/u-boot + Branch: master + +5. TI Linux Firmware: + Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git + Branch: ti-linux-firmware + +Build procedure: +---------------- +1. ATF: + +.. code-block:: text + + $ make CROSS_COMPILE=aarch64-none-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=lite SPD=opteed + +2. OPTEE: + +.. code-block:: text + + $ make PLATFORM=k3 CFG_ARM64_core=y CROSS_COMPILE=arm-none-linux-gnueabihf- CROSS_COMPILE64=aarch64-none-linux-gnu- + +3. U-Boot: + +* 3.1 R5: + +.. code-block:: text + + $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- am62x_evm_r5_defconfig O=/tmp/r5 + $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- O=/tmp/r5 + $ cd + $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- SOC=am62x SBL=/tmp/r5/spl/u-boot-spl.bin SYSFW_PATH=/ti-sysfw/ti-fs-firmware-am62x-gp.bin + +Use the tiboot3.bin generated from last command + +* 3.2 A53: + +.. code-block:: text + + $ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- am62x_evm_a53_defconfig O=/tmp/a53 + $ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- ATF=/build/k3/lite/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin DM=/ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f O=/tmp/a53 + +Target Images +-------------- +Copy the below images to an SD card and boot: + - tiboot3.bin from step 3.1 + - tispl.bin, u-boot.img from 3.2 + +Image formats: +-------------- + +- tiboot3.bin: + +.. code-block:: text + + +-----------------------+ + | X.509 | + | Certificate | + | +-------------------+ | + | | | | + | | R5 | | + | | u-boot-spl.bin | | + | | | | + | +-------------------+ | + | | | | + | |TIFS with board cfg| | + | | | | + | +-------------------+ | + | | | | + | | | | + | | FIT header | | + | | +---------------+ | | + | | | | | | + | | | DTB 1...N | | | + | | +---------------+ | | + | +-------------------+ | + +-----------------------+ + +- tispl.bin + +.. code-block:: text + + +-----------------------+ + | | + | FIT HEADER | + | +-------------------+ | + | | | | + | | A53 ATF | | + | +-------------------+ | + | | | | + | | A53 OPTEE | | + | +-------------------+ | + | | | | + | | R5 DM FW | | + | +-------------------+ | + | | | | + | | A53 SPL | | + | +-------------------+ | + | | | | + | | SPL DTB 1...N | | + | +-------------------+ | + +-----------------------+ diff --git a/doc/board/ti/index.rst b/doc/board/ti/index.rst index 014a097178..250d9242e8 100644 --- a/doc/board/ti/index.rst +++ b/doc/board/ti/index.rst @@ -8,3 +8,4 @@ Texas Instruments am335x_evm j721e_evm + am62x_sk